XR17C158 Exar Corporation, XR17C158 Datasheet - Page 17

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
The 8-bit Sleep register enables each UART sepa-
rately to enter Sleep mode. Sleep mode reduces
power consumption when the system needs to put
the UART(s) to idle. The UART enters sleep mode
when there is no interrupt pending. When all 8 UARTs
are put to sleep, the on-chip oscillator shuts off to fur-
ther conserve power. In this case, the octal UART is
awaken by any of the UART channel on from a re-
ceive data byte or a change on the serial port. The
UART is ready after 32 crystal clocks to ensure full
functionality. Also, a special interrupt is generated
with an indication of no pending interrupt. Logic 0 (de-
fault) is disable and logic 1 is enable to sleep mode.
There are 2 internal registers that provide device
identification and revision, DVID and DREV registers.
The 8-bit content in the DVID register provides device
identification. A return value of 0x28 from this register
indicates the device is a XR17C158. The DREV reg-
ister returns a 8-bit value of 0x01 for revision A with
0x02 equals to revision B and so forth. This informa-
tion is very useful to the software driver for identifying
which device it is communicating with and to keep up
with revision changes.
DVID [15:8] default 0x28)
Device identification for the type of UART. The upper
nibble indicates it is a XR17Cxxx series with lower
nibble indicating the number of channels.
Examples:
XR17C158 = 0x28
XR17C154 = 0x24
XR17C152 = 0x22
DREV [7:0] (default (0x01)
Revision number of the XR17C158. A 0x01 repre-
sents "revision-A" with 0x02 for rev-B and so forth.
1.2.6 SLEEP [31:24](default 0x00)
1.2.7 Device Identification and Revision
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7
Individual UART Channel Sleep Enable
Ch-6
PCI BUS OCTAL UART
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
SLEEP Register
17
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous
write to all 8 UARTs configuration register or individu-
ally. This is very useful for device intialization in the
power up and reset routines. Also, the register pro-
vides a facility to interface to the non-volatile memory
device such as a 93C46 EEPROM. In embedded ap-
plications, the user can use this facility to store propri-
etary data.
The 158 provides 8 multi-purpose inputs/outputs
[MPIO7:0] for general use. Each pin can be pro-
grammed to be an input or output function. The input
logic state can be set for normal or inverted level, and
optionally set to generate an interrupt. The outputs
can be set to be normal logic 1 or 0 state, or 3-state.
Their functions and definitions are programmed
through 5 registers: MPIOINT, MPIOLVL, MPIO3T,
MPIOINV and MPIOSEL. If all 8 pins are set for in-
puts, all 8 interrupts would be Or’ed together. The
Or’ed interrupt is reported in the channel 0 UART in-
terrupt status, see Interupt Status Register. The pins
may also be programmed to be outputs and to the 3-
state condition for signal sharing.
Bit 7 represents MPIO7 pin and bit 0 represents
MPIO0 pin. There are 5 registers that select, control
and monitor the 8 multipurpose inputs and outputs
pins.
REGB[16]
REGB[19:17]
REGB[20]
REGB[21]
REGB[22]
REGB[23]
1.2.8 RGEB Register
1.2.9 Multi-Purpose Inputs and Outputs
1.2.10 MPIO REGISTER
Figure 6
shows the internal circuitry.
Logic 0 (deafult) write to each UART
configuration registers individually.
Logic 1 enables simultaneous write to
all 8 UARTs configuration register.
Reserved
Control the EECK, clock, output (pin
116) on the EEPROM interface.
Control the EECS, chips select, output
(pin 115) to the EEPROM device.
EEDI (pin 114) data input. Write data to
the EEPROM device.
EEDO (pin 113) data output. Read data
from the EEPROM device.
PRELIMINARY