XR17C158 Exar Corporation, XR17C158 Datasheet - Page 16

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
TIMER [15:8] (default 0x00)
Reserved.
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The
least-significant bit of the timer is being bit [0] of the
Each bit selects 8X or 16X sampling rate for that
UART channel, bit-0 is channel 0. Logic 0 (default)
selects normal 16X sampling with logic one selects
8X sampling rate. Transmit and receive data rates will
double by selecting 8X.
TIMERCNTL [0]
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [4]
TIMERCNTL [7:5]
1.2.3 8XMODE [7:0] (default 0x00)
1.2.4 REGA [15:8] is reserved
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
Ch-7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Individual UART Channel 8X Clock Mode Enable
Ch-6
REGA [15:8]
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
8XMODE Register
TIMERMSB Register
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
Reserved (defaults to zero)
(default 0x00)
IS RESERVED
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2
Rsvd
16-Bit Timer/Counter Programmable Registers
T
(default 0x00)
ABLE
Rsvd
7: TIMER CONTROL R
Bit-9 Bit-8
Rsvd
TIMERCNTL Register
MPIO[0]
Control
16
Select
Clock
TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Reading the TIMERCNTL register will
clear its interrupt. Default value is zero upon pow-
erup and reset.
The 8-bit Reset register [RESET] provides the soft-
ware with the ability to reset the UART(s) when there
is a need. Each bit is self-resetting after it is written a
logic 1 to perform a reset to that channel. All registers
in that channel will be reset to the default condition,
see
nel 0 with bit-7=1 resets channel 7..
1.2.5 RESET [23:16] (default 0x00)
Bit-7
Re-trigger
Table 18
Ch-7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Single/
Bit-6
EGISTERS
Individual UART Channel Reset Enable
PCI BUS OCTAL UART
Ch-6
Bit-1 Bit-0
Start/
Stop
for details. Bit-0 =1 resets UART chan-
Bit-5
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
TIMERLSB Register
RESET Register
Enable
INT
Bit-4
Bit-3
Bit-2
XR17C158
Bit-1 Bit-0
REV. 1.0.0