AD9215-65 Analog Devices, AD9215-65 Datasheet - Page 9

• Manufacturer Part Number: AD9215-65
• Description: 10-Bit, 65/80/105 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

age. The minimum and maximum common-mode input levels
are defined as follows:
The minimum common-mode input level allows the AD9215 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input will accept the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9215 will then accept a signal varying between 2 V and 0 V.
In the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However,
the effect will be less noticeable at lower input frequencies.
DIFFERENTIAL INPUT CONFIGURATIONS
As previously detailed, optimum performance will be achieved
while driving the AD9215 in a differential input configuration.
For baseband applications, the AD8138 Differential Driver pro-
vides excellent performance and a flexible interface to the A/D
converter. The output common-mode voltage of the AD8138 is
easily set to AVDD/2, and the driver can be configured in a Sallen
Key filter topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9215. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 9.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
REV. PrA
Figure 9. Differential Transformer-Coupled Configuration
Figure 8. Differential Input Configuration Using the
AD8138
1V p-p
0.1 F
2V p-p
VCM
VCM
1k
1k
MIN
MAX
49.9
49.9
= VREF/2,
= (AVDD + VREF)/2.
523
499
0.1 F
AD8138
499
499
PRELIMINARY TECHNICAL DATA
R
R
C
C
R
R
C
C
VIN+
VIN–
AD9215
AGND
AVDD
VIN+
VIN–
AD9215
AGND
AVDD
–9–
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
SINGLE-ENDED INPUT CONFIGURATION
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration there will be a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source imped-
ances on each input are kept matched, there should be little effect
on SNR performance. Figure 10 details a typical single-ended
input configuration.
CLOCK INPUT AND CONSIDERATIONS
Typical high-speed A/D converters use both clock edges to
generate a variety of internal timing signals, and as a result may
be sensitive to clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic perfor-
mance characteristics. The AD9215 contains a clock duty
cycle stabilizer that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9215. As shown in TPC 20, noise
and distortion performance are nearly flat over a 30% range of
duty cycle.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency will require approximately 100 clock cycles
to allow the DLL to acquire and lock to the new rate.
High-speed, high-resolution A/Ds are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated with the following equation:
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and A/D aperture jitter specification. Under-
sampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9215.
Power supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
SNR degradation = 20 × log10 [1/2 × π × f
Figure 10. Single-Ended Input Configuration
2V p-p
49.9
INPUT
10 F
) due only to aperture jitter (t
10 F
0.1 F
0.1 F
R
R
C
C
A
, represents the root-
VIN+
VIN–
AD9215
AGND
AD9215
AVDD
INPUT
A
) can be
× t
A
]