AD9215-65 Analog Devices, AD9215-65 Datasheet - Page 12

• Manufacturer Part Number: AD9215-65
• Description: 10-Bit, 65/80/105 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

AD9215
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9215 can output data in either
offset binary or two’s complement format. There is also a provi-
sion for enabling or disabling the Clock Duty Cycle Stabilizer
(DCS). The MODE pin is a multilevel input that controls the
data format and DCS state. The input threshold values and
corresponding mode selections are outlined below.
–0.05
–0.10
–0.15
–0.20
–0.25
0.05
0.00
0.0
Figure 15. VREF Accuracy vs. Load
0.5
REFIN
10MHz
REFOUT
1.0
1V ERROR (%)
LOAD – mA
SIGNAL SYNTHESIZER
SIGNAL SYNTHESIZER
R AND S SMG, 2V p-p
R AND S SMG, 2V p-p
1.5
0.5V ERROR (%)
2.0
Figure 16. Evaluation Board Connections
2.5
BANDPASS
FILTER
3.0
XFMR
INPUT
CLOCK
–12–
–
3V
AVDD DUT
MODE
Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
The MODE pin is internally pulled down to AGND by a
20 kΩ resistor.
EVALUATION BOARD
The AD9215 evaluation board provides all of the support
circuitry required to operate the A/D in its various modes and
configurations. The converter can be driven differentially,
through an AD8138 driver or a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 16 shows the typical bench characterization setup used to
evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (< 1 picosecond rms
jitter) be used to realize the ultimate performance of the con-
verter. Proper filtering of the input signal, to remove harmonics
and lower the integrated noise at the input, is also necessary to
achieve the specified noise performance.
Complete schematics and layout plots follow, which demon-
strate the proper routing and grounding techniques that should
be applied at the system level.
+
AVDD
EVALUATION BOARD
–
3V
GND GND DUT
AD9215
+
–
3V
DRVDD
+
Table III. Mode Selection
–
3V
DVDD
Data
Format
Two’s Complement
Two’s Complement
Offset Binary
Offset Binary
+
J1
PROCESSING
CAPTURE
DATA
AND
Duty Cycle
Stabilizer
Disabled
Enabled
Enabled
Disabled
REV. PrA