AD9215-65 Analog Devices, AD9215-65 Datasheet - Page 8

• Manufacturer Part Number: AD9215-65
• Description: 10-Bit, 65/80/105 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

AD9215
APPLYING THE AD9215
THEORY OF OPERATION
The AD9215 architecture consists of a front-end Sample and
Hold Amplifier (SHA) followed by a pipelined switched capaci-
tor A/D converter. The pipelined A/D converter is divided into
two sections, consisting of seven 1.5-bit stages and a final 3-bit
flash. Each stage provides sufficient overlap to correct for flash
errors in the preceding stages. The quantized outputs from
each stage are combined into a final 10-bit result in the digi-
tal correction logic. The pipelined architecture permits the
first stage to operate on a new input sample while the remain-
ing stages operate on preceding samples. Sampling occurs on
the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each one of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction and passes the data to the output buffers. The output
buffers are powered from a separate supply allowing adjustment
of the output voltage swing. During power-down the output
buffers go into a high impedance state.
ANALOG INPUT
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range and maintain excellent
performance, as shown in Figure 7. An input common-mode
voltage of midsupply will minimize signal-dependant errors and
provide optimum performance.
Referring to Figure 6, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half of
a clock cycle. A small resistor in series with each input can help
reduce the peak transient current required from the output stage
of the driving source. Also, a small shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network will create a low-pass filter at the A/D’s input;
therefore, the precise values are dependant upon the applica-
tion. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the A/D.
PRELIMINARY TECHNICAL DATA
–8–
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the A/D core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section. Maxi-
mum SNR performance will be achieved with the AD9215 set
to the largest input span of 2 V p-p. The relative SNR degradation
will be 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
Figure 7. AD9215-105: SNR, THD vs. Common-Mode Level
VIN+
VIN–
90
85
80
75
70
65
60
55
50
0
REFT = 1/2 (AVDD + VREF),
REFB = 1/2 (AVDD – VREF)’
Span = 2 × (REFT – REFB) = 2 × VREF
C
C
Figure 6. Switched-Capacitor SHA Input
PAR
PAR
0.5
T
T
COMMON MODE LEVEL – V
1.0
SNR 35MHz 2V DIFF
SNR 2.5MHz 2V DIFF
SFDR 35MHz 2V DIFF
0.5pF
0.5pF
1.5
SFDR 2.5MHz 2V DIFF
2.0
T
T
2.5
H
H
3.0
REV. PrA
–90
–85
–80
–75
–70
–65
–60
–55
–50