USBLC6-2 STMicroelectronics, USBLC6-2 Datasheet - Page 5

• Manufacturer Part Number: USBLC6-2
• Description: VERY LOW CAPACITANCE ESD PROTECTION
• Manufacturer: STMicroelectronics

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USBLC6-2
2.3
Figure 7.
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see
protection).
Figure 6.
How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
possible to avoid overvoltages due to parasitic phenomena (see
layout consideration)
ESD behavior: layout optimization
Unsuitable layout
Optimized layout
1 1
2
3
1 1
2
3
V
V
V
CL
CL-
ESD surge on data line
TRANSIL
+ = V
ESD behavior: parasitic phenomena due to unsuitable layout
= -V - L
TRANSIL
F
=
L
I/O
I/O
V
BR
I/O pin
6
5
4
6
5
4
di
dt
+ V + L
+
CC
L
- L
Rd.Ip
F
I/O
GND
di
dt
to V
I/O
L
L
V
di
dt
VBUS
GND
F
di
dt
BUS
+ L
V
GND
GND pin
CC
V
L
pin and from GND plane to GND pin must be as short as
TRANSIL
GND
pin
di
dt
dt
di
Figure 8.
surge > 0
surge > 0
V
CL
V
Data line
BUS
ESD SURGE
L
-L
I/O
I/O
V
ESD behavior: measurement
conditions
di
dt
di
dt
TRANSIL
+ L
- L
GND
GND
+ V
- V
di
dt
di
dt
F
IN
F
TEST BOARD
2.3: How to ensure good ESD
t = 1 ns
t = 1 ns
r
r
V
V
CL-
CL+
Figure 6.
Technical information
Negative
Positive
OUT
Surge
Surge
and
Figure 7.
t
t
+5 V
5/14
for