GS1559-CBE2 Gennum Corp., GS1559-CBE2 Datasheet - Page 32

• Manufacturer Part Number: GS1559-CBE2
• Description: HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver
• Manufacturer: Gennum Corp.

4.6.2 Master Mode
4.6.3 Slave Mode
For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED
output signal HIGH if (1) the reclocker has locked to the input data stream as
indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have
been correctly identified.
If after four attempts lock has not been achieved, the lock detection algorithm will
enter into PLL lock mode. In this mode, the reclocker will attempt to lock to the input
data stream without detecting SMPTE TRS or DVB-ASI sync words. This
unassisted process can take up to 10ms to achieve lock.
When reclocker lock as indicated by the internal pll_lock signal is achieved in this
mode, one of the following will occur:
1. In slave mode, data will be passed directly to the parallel outputs without any
2. In master mode, the LOCKED signal will be asserted LOW, the parallel
Recall that the GS1559 is said to be in master mode when the MASTER/SLAVE
input signal is set HIGH. In this case, the following four device pins become output
status signals:
•
•
•
•
The combined setting of these four pins will indicate whether the device has locked
to valid SMPTE or DVB-ASI data at SD or HD rates.
combinations.
The GS1559 is said to be in slave mode when the MASTER/SLAVE input signal is
set LOW. In this case, the four device pins listed in
control signals.
It is required that the application layer set the first three inputs to reflect the
appropriate input data format (SMPTE_BYPASS, DVB_ASI, and SD/HD). If just
one of these three is configured incorrectly, the device will not lock to the input data
stream, and the DATA_ERROR pin will be set LOW.
The fourth input signal, RC_BYP, allows the application layer to determine whether
the serial digital loop-through output will be a reclocked or buffered version of the
input, (see
formats.
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further processing taking place and the LOCKED signal will be asserted HIGH
if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW; or
outputs will be latched to logic LOW, and the SMPTE_BYPASS and DVB_ASI
output signals will also be set LOW.
SMPTE_BYPASS
DVB_ASI
SD/HD
RC_BYP
Section
4.4.2).
Table 4-3
30572 - 1
shows the required settings for various input
GS1559 Preliminary Data Sheet
November 2004
Section 4.6.2
Table 4-2
shows the possible
become input
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