CMX138 CML Microcircuits, CMX138 Datasheet - Page 32

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
7.9
The CMX138 includes a 2-pin crystal oscillator circuit. This can either be configured as an oscillator, as
shown in Figure 2, or the XTAL input can be driven by an externally generated clock. The crystal (Xtal)
source frequency can go up to 12.288MHz (clock source frequency up to 24.576MHz), but a 6.144MHz or
3.6864MHz Xtal is assumed for the default functionality provided in the CMX138 (see section 7.1).
7.9.1
A PLL is used to create the Main Clock (nominally 24.576MHz) for the internal sections of the CMX138.
At the same time, other internal clocks are generated by division of either the XTAL Reference Clock or
the Main Clock. These internal clocks are used for determining the sample rates and conversion times of
A-to-D and D-to-A converters, running a General Purpose Timer and the signal processing block. It
should be noted that in IDLE mode the setting of the GP Timer divider directly affects the C-BUS latency
(with the default values this is nominally 250μs).
The CMX138 defaults to the settings appropriate for a 6.144MHz or 3.6864MHz Xtal, however if other
frequencies are to be used (to facilitate commonality of Xtals between the external RF synthesizers and
the CMX138 for instance) then the Program Block registers P3.2 to P3.6 will need to be programmed
appropriately at power-on. A table of common values is provided in Table 1. The C-BUS registers $BC
and $BD are controlled automatically and must not be accessed directly by the user.
See:
© 2008 CML Microsystems Plc
OSC
o
Digital System Clock Generator
Main Clock Operation
Program Block 3 – AuxDAC, RAMDAC and Clock control:
Ref CLK div
Ref CLK div
$AC b0-8
$BD b0-8
/1 to 512
/1 to 512
3.0 - 24.576MHZ Clock
3.0 - 12.288MHz Xtal
or
SysCLK1
MainCLK
Ref
Ref
48 - 192kHz
48 - 192kHz
(96kHz typ)
(96kHz typ)
PD
PD
Figure 15 Digital Clock Generation Schemes
SysCLK1
MainCLK
Div
Div
/1 to 1024
/1 to 1024
$AB b0-9
$BC b0-9
PLL div
PLL div
LPF
LPF
Page 32
VCO
VCO
(49.152MHz typ)
(49.152MHz typ)
MainCLK VCO
SysCLK1 VCO
$AC b11-15
98.304MHz
98.304MHz
$BD b11-15
SysCLK1
Pre-CLK
MainCLK
24.576-
Pre-CLK
24.576-
AuxADC
Div
$AB b10-15
$BC b10-15
VCO op div
VCO op div
/1 to 64
/1 to 64
ADC / DAC
(83.3kHz typ)
To Internal
dividers
Aux_ADC
D/138_FI1.0/5
(24.576MHz typ)
384kHz-20MHz
384kHz-50MHz
SysCLK1
MainCLK
CMX138
Output
Output