CMX138 CML Microcircuits, CMX138 Datasheet - Page 13

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
7
7.1
The CMX138 is designed to work with a Xtal or external frequency source of 6.144MHz or 3.6864MHz (as
selected by the state of the CLKSEL pin). If either of these default configurations is not suitable, then
Program Register Block 3 should to be loaded with the correct values to ensure that the device will work
to specification with the user specified clock frequency. A table of common values can be found in Table
1. Note the maximum Xtal frequency is 12.288MHz, although an external clock source of up to
24.576MHz can be used.
The register values in Table 1 are shown in hex (however only the lower 10 bits are relevant), the default
settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable
limits) are in italics. The new P3.2-3 settings take effect following the write to P3.3 (the settings in P3.4-7
are implemented on a change to Rx or Tx mode). Check that the PRG flag is set in the Status register
($C6 bit 0 is set to '1') before writing each new P3.2 – P3.7 value via the Programming register ($C8). If a
default frequency is not used, the register values in Table 1 should be programmed into the CMX138
immediately after power-up.
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
7.2
A serial data interface (C-BUS) is used for command, status and data transfers between the CMX138 and
the host µC; this interface is compatible with microwire, SPI. Interrupt signals notify the host µC when a
change in status has occurred and the µC should read the status register across the C-BUS and respond
accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 8.1.1.
7.2.1
This block provides for the transfer of data and control or status information between the CMX138’s
internal registers and the host µC over the C-BUS serial interface. Each transaction consists of a single
Address byte sent from the µC which may be followed by one or more Data byte(s) sent from the µC to be
written into one of the CMX138’s Write Only Registers, or one or more data byte(s) read out from one of
the CMX138’s Read Only Registers, as illustrated in Figure 4.
Data sent from the µC on the Command Data line is clocked into the CMX138 on the rising edge of the
Serial Clock input. Reply Data sent from the CMX138 to the µC is valid when the Serial Clock is high.
The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS
interface is compatible with most common µC serial interfaces and may also be easily implemented with
general purpose µC I/O pins controlled by a simple software routine.
© 2008 CML Microsystems Plc
Connect CLKSEL pin to:
Program Register
Detailed Descriptions
Xtal Frequency
Host Interface
C-BUS Operation
DAC clk divide
Internal ADC /
PLL clk divide
Ref clk divide
and AUX clk
and AUX clk
VCO output
VCO output
GP Timer
divide
divide
Table 1 Xtal/clock frequency settings for Program Block 3
3.579
$017
$085
$043
$398
$140
$008
DV
SS
3.6864
$1E0
$017
$085
$024
$140
$008
DV
SS
6.144
DV
$018
$088
$040
$200
$140
$008
DD
Page 13
External frequency source (MHz)
9.0592
$0C6
DV
$018
$10F
$370
$140
$008
DD
$07D
DV
$019
$10F
$200
$140
$008
12.0
DD
$0C8
DV
$019
$110
$300
$140
$008
12.8
DD
16.368
DV
$018
$095
$155
$400
$140
$008
DD
$15E
DV
$019
$115
$400
$140
$008
16.8
D/138_FI1.0/5
DD
CMX138
$0C8
DV
$018
$099
$200
$140
$008
19.2
DD