CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet
CD016G0PFA
Related parts for CD016G0PFA
CD016G0PFA Summary of contents
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S29CD016G 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Data Sheet Distinctive Characteristics Architecture Advantages Simultaneous Read/Write operations — Data can be read from one bank while executing erase/program functions in ...
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General Description The S29CD016G Megabit, 2.5 Volt-only single power supply burst mode flash memory device. The device can be configured for 524,288 double words. The device can also be programmed in standard EPROM programmers. To eliminate bus ...
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status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased ...
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Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6 Block Diagram . . . . . . . . . . ...
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mand ......................................................................................................... 56 SecSi Sector Protection Bit Program Command ........................ 56 PPB Lock Bit Set Command .............................................................. 56 DYB Write Command ........................................................................ 57 Password Unlock Command ............................................................. 57 PPB Program Command ..................................................................... 57 ...
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Product Selector Guide Part Number Standard Voltage Range 2.5 – 2. Speed Option (Clock Rate) Max Initial/Asynchronous Access Time ACC Max Burst Access Delay (ns) Max Clock Rate (MHz) Min Initial Clock Delay ...
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Block Diagram WE# RESET# State ACC Control WP# Command WORD# Register CE# OE Detector ADV# Burst State CLK Control WAIT# DQ0–DQ15 A0–A18 March 22, 2004 S29CD016_00A0 I ...
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Block Diagram of Simultaneous Read/Write Circuit A0–A18 A0–A18 STATE RESET# CONTROL & WE# COMMAND CE# REGISTER ADV# DQ0–DQ31 A0–A18 ...
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Connection Diagrams DQ16 1 DQ17 2 DQ18 3 DQ19 CCQ DQ20 7 DQ21 8 DQ22 9 DQ23 10 DQ24 11 DQ25 12 DQ26 13 DQ27 14 V ...
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Connection Diagrams MCH ACC A9 A10 A12 A11 CC ...
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Pin Configuration A0–A18 DQ0–DQ31 CE# OE# WE RY/BY# CLK ADV# IND# WAIT# WP# ACC CCQ V CC RESET# MCH March 22, 2004 S29CD016_00A0 ...
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Logic Symbols x32 Mode A0–A18 DQ0–DQ31 CLK CE# OE# WE# IND/WAIT# RESET# ADV# RY/BY# ACC WP ...
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... F = Ball Fortified Ball Grid Array, 1.0 mm pitch package CLOCK FREQUENCY MHz MHz MHz Clock Frequency QAI00 QAI01 QAN00 QAN01 Package Marking CD016G0PFA FAI00 FAI01 CD016G0MFA FAN00 FAN01 CD016G0JFA Valid Combinations S29CD016G ° ° +85 C) ° ° +125 ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of ...
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VersatileI/O™ Control IO The VersatileI/O (V the device generates at its data outputs and the voltages tolerated at its data in- puts to the same voltage level that is asserted on ...
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Table 2. Bank Bank 0 Bank 1 Also Table 18. ”Allowed Operations During Erase/Program Suspend. Also Table ...
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“Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The ...
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OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at Vcc ± 0.2 V. The device requires standard ...
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primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When ...
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CE# CLK ADV# Addresses Address 0 Address 1 Data D0 OE# WE Float IND/WAIT Note: Operation is shown for the 32-bit data bus. Synchronous (Burst) Read Operation The device is capable of performing burst read operations ...
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Table 6. 32- Bit Linear and Burst Data Order Data Transfer Sequence (Independent of the WORD# pin) Two Linear Data Transfers Four Linear Data Transfers Eight Linear Data Transfers March 22, 2004 S29CD016_00A0 ...
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CE# Control in Linear Mode The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken any time during ...
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CE CLK ADV# Address 1 Latched Addresses Address 1 Data OE# IND/WAIT# Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay config- ...
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CR13 CR12 1st CLK CLK ADV# Address 1 Latched Addresses Valid Address 3 DQ31-DQ0 4 DQ31-DQ0 5 DQ31-DQ0 Notes: 1. Burst access starts with ...
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Configuration Register The device contains a Configuration Register for configuring read accesses. The Configuration Register is accessed by the Configuration Register Read and the Configuration Register Write commands. The Configuration Register does not ...
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Table 9. Configuration Register Definitions (Continued) CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0) Speed Options 54D, 64C, 65A: 0000 = 2 CLK cycle initial burst access delay 0001 = 3 CLK cycle initial burst access delay 0010 = 4 ...
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Table 10. Configuration Register After Device Reset CR15 CR14 CR13 RM Reserve IAD3 1 0 CR7 CR6 CR5 BS CC Reserve 1 1 Initial Access Delay Configuration The frequency configuration informs the device ...
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It is important to remember that setting either the Persistent Sector Protec- tion Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode not possible to switch between the two methods once a locking ...
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the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB ...
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DYB PPB Table 11 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, ...
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64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is ...
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Write Protect (WP#) The device features a hardware protection option using a write protect pin that prevents programming or erasing, regardless of the state of the sector’s Persis- tent or Dynamic Protection Bits. The WP# pin is associated with the ...
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Executing the Chip Erase command is permitted when the SecSi Sector is en- abled. The Chip Erase command erases all sectors in the memory array except for sector 0 in top-bootblock configuration ...
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Logical Inhibit Write cycles are inhibited by holding any one of OE initiate a write cycle, CE# and WE# must be a logical zero ( logical one (V Power-Up Write ...
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March 22, 2004 S29CD016_00A0 S29CD016G 35 ...
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Table 12. Sector Addresses for Ordering Option 00 Sector Sector Group SA0 (Note 1) SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 ...
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Table 12. Sector Addresses for Ordering Option 00 (Continued) Sector Sector Group SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 ...
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Table 13. Sector Addresses for Ordering Option 01 Sector Sector Group SA0 (Note 1) SG0 SA1 (Note 1) SG1 SA2 SG2 SA3 SG3 SA4 SG4 SA5 SG5 SA6 SG6 SA7 SG7 SA8 SA9 SG8 SA10 SA11 SA12 SG9 SA13 SA14 ...
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Table 13. Sector Addresses for Ordering Option 01 (Continued) Sector Sector Group SA31 SA32 SG14 SA33 SA34 SA35 SA36 SG15 SA37 SA38 SG16 SA39 SG17 SA40 SG18 SA41 SG19 SA42 SG20 SA43 SG21 ...
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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. Software support can then be device-independent, ...
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Addresses Data 1Bh 0023h 1Ch 0027h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 0009h 22h 0000h 23h 0005h 24h 0000h 25h 0007h 26h 0000h March 22, 2004 S29CD016_00A0 ...
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Addresses Data 27h 0015h 28h 0003h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0003h 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 001Dh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h 0000h 37h 0020h 38h 0000h 39h 0000h ...
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Table 17. CFI Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0004h 46h 0002h 47h 0001h 48h 0000h 49h 0006h 4Ah 001Fh 4Bh 0001h ...
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Table 17. CFI Primary Vendor-Specific Extended Query (Continued) Addresses Data 4Fh 0001h 50h 0001h 51h 0000h 57h 0002h 58h 000Fh 59h 001Fh 5Ah 0000h 5Bh 0000h ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Tables 19-20 define the valid register com- mand sequences. Writing incorrect address and data values or ...
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Configuration Register definition. The Burst read cycle consists of an address phase and a corresponding data phase. During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock period. Together ...
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mand. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further con- trols or timings. The device automatically generates ...
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Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 18 ...
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The following four sections describe the commands that may be executed within the unlock bypass mode. Unlock Bypass Program Command The Unlock Bypass Program command is a two-cycle command that consists of the ...
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The command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse (whichever ...
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dow has expired. The status of the sector erase operation is determined three ways: Data# polling of the DQ7 pin Checking the status of the toggle bit DQ6 Checking the status of the ...
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Sector Erase and Program Suspend Operation Mechanics A successful erase pulse has a duration or 1.2 ms number of previous erase cycles (among other factors). A successful sector erase operation requires 300 successful erase pulses. An internal counter monitors the ...
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from a non-busy (non-erasing) sector (stored data is read). No bits are toggled during program suspend mode. Software must keep track of the fact that the de- vice suspended mode. ...
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The Configuration Register Read Command is fully operational if the SecSi sector is enabled. Common Flash Interface (CFI) Command The Common Flash Interface (CFI) command provides device size, geometry, and capability information directly to the users system. Flash devices that ...
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The following commands are unavailable when the SecSi sector is enabled. Issu- ing the following commands while the SecSi sector is enabled results in the command being ignored. 1. Unlock Bypass 2. CFI ...
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Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking ...
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The PPB Lock Bit Set command is permitted if the SecSi sector is enabled. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. ...
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PPB Program command will not execute and the command will time-out without programming the PPB. The host system must determine whether a PPB has been fully programmed by noting the status of DQ0 in the sixth cycle ...
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PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Non-volatile Protection Bit ...
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Table 19. Memory Array Command Definitions (x32 Mode) Command (Notes) Read (5) 1 Reset (6) 1 Manufacturer ID 4 Autoselect (7) Device ID (11) 6 Program 4 Chip Erase 6 Sector Erase 6 Program/Erase Suspend (12) 1 Program/Erase Resume (13) ...
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Table 20. Sector Protection Command Definitions (x32 Mode) Command (Notes) Addr Data Addr Data Reset 1 XXX SecSi Sector Entry 3 555 SecSi Sector Exit 4 555 SecSi Protection Bit Program 6 555 ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 21 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each ...
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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is ...
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RY/BY#: Ready/Busy# The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output is low, the device is ...
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program address falls within a protected sector, DQ6 toggles for approxi- mately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during ...
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The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition ...
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Absolute Maximum Ratings Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . ...
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Characteristics CMOS Compatible Parameter Description I Input Load Current LI I WP# Input Load Current LIWP I A9, ACC Input Load Current LIT I Output Leakage Current LO V Active Burst Read ...
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DC Characteristics (continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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Test Conditions Note: Diodes are IN3064 or equivalent Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels ...
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AC Characteristics V and V Power- Parameter Description t V Setup Time VCS Setup Time VIOS IO t RESET# Low Hold Time RSTH IOP RESET# Figure 14 ...
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Characteristics Asynchronous Read Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ...
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AC Characteristics Burst Mode Read Parameter JEDEC Std. Description t Burst Access Time Valid Clock to Output Delay BACC t ADV# Setup Time to Rising Edge of CLK ADVCS t ADV# Hold Time from Rising Edge of CLK ADVCH t ...
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Characteristics CE# CLK t ADVCS ADV# t ACS Addresses Aa t ACH Data OE#* IND# March 22, 2004 S29CD016_00A0 CES ...
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AC Characteristics CLK ADV# CE# Addresses Data WE# OE# IND/WAIT# Figure 17. Asynchronous Command Write Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access ...
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Characteristics Hardware Reset (RESET#) Parameter JEDEC Std. Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to ...
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AC Characteristics Data WE# WP# RY/BY Program/Erase Command WPWS Valid WP Figure ...
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Characteristics Erase/Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Note program address program data ...
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Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE# OE# WE Data RY/BY# t VCS V CC Note sector address (for Sector Erase ...
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AC Characteristics t RC Addresses VA t ACC OE# t OEH WE# DQ7 Data t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an ...
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AC Characteristics V IH RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# * Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah. ** Command for sector protect ...
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Characteristics Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX ...
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AC Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Double Word Program Time Accelerated Double Word Program Time Accelerated Chip Program Time Chip Program Time x32 (Note 3) Notes: 1. Typical ...
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Physical Dimensions PRQ080–80-Lead Plastic Quad Flat Package PIN S D3 PIN ONE I.D. -A- SEE NOTE 3 PIN P -D- SEE DETAIL X e BASIC A2 A1 PACKAGE PQR 080 JEDEC MO-108(B)CB-1 SYMBOL MIN NOM MAX ...
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Physical Dimensions LAA080–80-ball Fortified Ball Grid Array ( mm CORNER ID. (INK OR LASER) 1.00±0.5 TOP VIEW A1 CORNER SIDE VIEW PACKAGE LAA ...
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Revision Summary Revision A (March 22, 2004) Performance Characteristics Burst Mode Read: changed to 66-MHz. Ordering Information Changed device number/description callout to show the two 16-Mbit configurations. Table 12 and Table 13 Corrected which sectors report to which bank. Asynchronous ...