STG4260 ST Microelectronics, Inc., STG4260 Datasheet
STG4260
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STG4260 Summary of contents
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... This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Low voltage 0.5 Ω dual SPDT switch with Description The STG4260 is a high -speed CMOS low voltage dual analog SPDT (single pole dual throw) switch or 2:1 multiplexer/demultiplexer switch fabricated 2 in silicon gate C to operate from 1 ...
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... Contents Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 STG4260 ...
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... STG4260 1 Pin settings 1.1 Pin connections Figure 1. Pin connection 1.2 Pin description Table 2. Pin assignment Pin number Symbol Name and function SEL2 Selection control for switch 2 V Logic supply voltage L SEL1 Selection control for switch 1 1S1 Independent channel for switch 1 ...
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... Logic diagram 2 Logic diagram Figure 2. Functional diagram Figure 3. Circuit equivalent logic Table 3. Truth table SEL High impedance 4/19 SEL1 1S1 D1 1S2 2S1 D2 2S2 SEL2 Switch S1 ON (1) OFF STG4260 S2 S1 Switch S2 (1) OFF ON ...
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... STG4260 3 Maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied ...
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... A Min Typ Max Min 1.25 1.25 1.75 1.75 2.34 2.34 2.80 2.80 0.6 0.8 1.05 1.5 1.5 2.5 0.75 1.0 0.50 0.65 0.45 0.55 0.40 0. 1000 1700 300 430 170 220 160 210 160 210 CC -30 30 -300 CC CC -30 30 -300 -30 30 -300 CC STG4260 Unit Max V 0.6 0.8 V 1.05 1.5 3.7 1.3 Ω 0.8 0.7 0.65 mΩ 2000 550 270 mΩ 270 270 300 nA 300 nA 300 nA ...
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... STG4260 Table 6. DC specifications (continued) V Symbol Parameter (V) Quiescent I 1.65 – 4.3 CC supply current SEL leakage I 1.65 – 4.3 SEL current 1. Δ ON(Max) ON(Min) 2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Table 7. AC electrical characteristics (C ...
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... 4 600 kHz Ω 4.3 L 4.3 = output input to off switch D S ≤5 ns) (continued Value T = 25°C -40 to 85°C A Min Typ Max Min 83 98 114 140 0.01 50 STG4260 Unit Max MHz ...
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... STG4260 Table 8. Capacitive characteristics Symbol Parameter Control pin C input 1.8 – 4.3 1.8 – 4.3 V SEL capacitance Sn port C 1.8 – 4.3 SN capacitance D port capacitance C 1.8 – 4.3 1.8 – 4 when the switch is enabled Test condition (V) ( 1.8 – 4 Electrical characteristics Value °C - °C ...
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... Test circuits 5 Test circuits Figure 4. ON resistance Figure 5. Bandwidth 10/ GND GND GND STG4260 D CS14071 D V OUT CS00371 ...
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... STG4260 Figure 6. OFF leakage V SS Figure 7. Channel-to-channel crosstalk S(OFF GND Test circuits I D(OFF CS14081 CS14091 11/19 ...
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... Test circuits Figure 8. OFF isolation V S Figure 9. Test circuit 5/ equivalent: (includes jig capacitance Ω or equivalent pulse generator (typically 50 Ω OUT 12/ GND GND STG4260 V OUT 50 Ω CS00381 ...
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... STG4260 Figure 10. Break-before-make time delay Figure 11. Switching time and charge injection ( GEN GEN Figure 12. Turn ON, turn OFF delay time = 0 Ω MΩ 100 pF Test circuits 13/19 ...
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... Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com. Figure 13. Flip-chip 12 mechanical outline 14/19 STG4260 ® 8098886_F ...
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... STG4260 Table 9. Flip-chip 12 mechanical data Symbol ccc Figure 14. Footprint recommendation Millimeters Min Typ 0.535 0.58 0.18 0.205 0.355 0.375 0.215 0.255 1.85 1.9 1.5 0.45 0.5 1.35 1.4 1 0.25 0.19 0.2 0.08 Package mechanical data Max 0.625 0.23 0.395 0.295 1.95 0.55 1.45 0.21 8098886_F 15/19 ...
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... Package mechanical data Figure 15. Flip-chip 12 tape information Figure 16. Flip-chip 12 tape orientation 16/19 STG4260 ...
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... STG4260 Figure 17. Reel information Package mechanical data 17/19 ...
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... Revision history 7 Revision history Table 10. Document revision history Date 19-Nov-2008 18/19 Revision 1 Initial release. STG4260 Changes ...
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... STG4260 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...