CS2411 Amphion, CS2411 Datasheet - Page 7

• Manufacturer Part Number: CS2411
• Description: User-programmable Fft/ifft 1024-point Block Based
• Manufacturer: Amphion

CS2411 keeps track of the numeric values during the
transform computation. If overflow occurs, due to the
insufficient number of shifting down bits programmed for the
given input data, the overflow value is saturated and the
overflow flag signal (YOV) is asserted to alert the application
system.
The overflow signal is flagged on-the-fly when the
computation is in progress. It is automatically reset when a
new transform is started.
The processing time starts from when the last data of a data
block is loaded into the core to when the transform has been
completed and is a function of the transform size. It is
equivalent to the time interval from when output signal Busy
is asserted to when it is de-asserted and is measured in
For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers application
specific silicon cores that are pre-optimized to a targeted silicon technology by Amphion experts.
Consult your local Amphion representative for product specific performance information, current availability of individual
products, and lead times on ASIC core porting.
For ASIC prototyping or for projects requiring the fast time-to-market of a programmable logic solutions that offer the silicon-
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* The implementation information on ALTERA devices is available upon request.
PRODUCT ID
CS2411XV*
PRODUCT
CS2411TK
PROCESSING TIME AND LATENCY
ID#
OVERFLOW HANDLING
VENDOR
VENDOR
SILICON
SILICON
TSMC
Xilinx
AVAILABILITY AND IMPLEMENTATION INFORMATION
PROGRAMMABLE
standard Cell libraries
LOGIC PRODUCT
180 nm using Artisan
PROCESS
Virtex-E
PROGRAMMABLE LOGIC CORES
Table 9: Programmable Logic Cores
Table 8: CS2411 ASIC Core
FREQUENCY (MHz)
ASIC CORES
MAXIMUM
FREQUENCY
MAXIMUM
57
108 MHz
number of clock cycles listed. The real transform time
depends on the clock frequency.
The transform period includes the transform time and the
data I/O time. It indicates the number of clock cycles required
for the core to perform one transform with input data loading
and transform result downloading. The minimum transform
period is obtained by asserting input signal YEnab as soon as
the output signal Done is asserted and by starting the next
data block as soon as output signal BUSY returns to LOW.
Table 7 lists the transform time and minimum period for the
transform size of 1024.
Transform
Table 7: CS2411 Processing Time and Transform Period
1024-point
Size
USED (LOGIC)
RESOURCES
1639 Slices
DEVICE
Processing Time
GATES
LOGIC
(Clock cycles)
34K
4096
USED (MEMORY)
MEMORY
Port RAM
51K Dual
RESOURCES
AREA
9 BRAMs
DEVICE
Minimum Transform
(Clock cycles)
AVAILABILITY
Period
5120
AVAILABILITY
Now
Now
7
TM