CS2411 Amphion, CS2411 Datasheet - Page 3

• Manufacturer Part Number: CS2411
• Description: User-programmable Fft/ifft 1024-point Block Based
• Manufacturer: Amphion

The CS2411 performs a mixed decimation in frequency (DIF),
radix-4, forward or inverse Fast Fourier Transforms on a 1024-
point complex data block. The transform is scheduled in four
computation passes. Data is loaded into the core in normal
sequential (natural) order. The transform result comes out
from the core in the natural order also. The core is on-line
programmable on the transform type and scaling down
control. The input and output data and the twiddle factor
wordlengths have been chosen such that it can be used in a
wide range of applications such as audio, video and
communications.
The core computes the transform using fixed-point arithmetic
with programmable shift down control on each computation
passes to handle the possible wordlength growth and
overflow in the transform. This achieves the maximal
accuracy possible while maintaining the desired dynamic
range for the output. The core is a synchronous design with all
the flip-flops being triggered at the rising edge of the clock
signal CLK.
Programming CS2411 is performed when the core is
synchronously reset. This is done through asserting signal
CLR and applying appropriate signals to the input ports IFFT
and SDC. Port IFFT specifies the transform type i.e. FFT/IFFT
Table 2 lists the FFT/IFFT value for programming the core to
appropriate transform type.
Done
YBS
YAV
YRe
YIm
YOV
Name
PROGRAMMING THE CORE
I/O Width
O
O
O
O
O
O
13
13
1
1
1
1
Output signal indicating the transform result is available. It goes to HIGH when the core is ready to
output transform result and returns to LOW when YEnab is asserted to download the result.
Output data Y block start signal, active HIGH, asserted when the first data of the 1024-point trans-
formed block is available on the output port. The remaining data of the 1024-point transform result is
available at the output of the core in the following clock cycles in natural order.
Output data Y available indicator, active HIGH, asserted with valid data of the 1024-point transform
result
Real component of output data Y, in two’s complement format, valid only when YAV is HIGH
Imaginary component of output data Y, in two’s complement format, valid only when YAV is HIGH
Output data Y overflow signal, active HIGH, asserted when overflow occurs when the transform is
performed. It is reset when a new transform starts and is associated with the 1024-point block.
Table 1: CS2411 - 1024 Point FFT / IFFT Interface Signal Definitions
FUNCTIONAL DESCRIPTION
The core performs 4-bit unconditional shifting down on the
internal data during the 1024-point transform. However,
theoretically the 1024-point FFT may have up to a total of 11-
bits word growth. The CS2411 core can perform up to 4-bit
unconditional shifting down and 7-bit controlled shifting
down operation to avoid possible overflow and also to allow
the transform gain to be controlled. This is programmed
through port SDC. The total number of shift down bits
decides the transform scaling down factor. Table 3 lists the
SDC values for programming the scaling factor.
Port SDC
Description
000
001
010
011
100
101
110
111
Table 2: Programming Transform Type
Port IFFT
Table 3: Programming Scaling Factor
0
1
Shifting
Fixed
(Bits)
4
4
4
4
4
4
4
4
Additional
Shifting
Transform Type
(Bits)
0
1
2
3
4
5
6
7
IFFT
FFT
(2
Scaling
Factor
1/1024
1/2048
1/128
1/256
1/512
-(7+SDC)
1/16
1/32
1/64
)
3
TM