CS2411 Amphion, CS2411 Datasheet - Page 4

• Manufacturer Part Number: CS2411
• Description: User-programmable Fft/ifft 1024-point Block Based
• Manufacturer: Amphion

After the global asynchronous reset signal, RST is applied, the
core is reset to the default mode: 1024-point FFT without the
additional shifting operation. Programming the core can be
performed at any time subsequently. The programming
signals are valid only when CLR is asserted. This is illustrated
in Figure 3. It is noted that when CLR is applied the core is
reset as well.
Figure 3: Configuration Timing
The input complex number data is represented by 13-bit real
and imaginary components, namely XRe and XIm, in the
two's complement format. The input data is loaded into the
core in the normal order, i.e., X(0) enters the core first,
followed by X(1) in the next clock cycle, and then X(2) in the
following cycle, etc. In total it takes 1024 clock cycles for a data
block to enter the core for FFT/IFFT processing.
which consist of a 13-bit real component YRe and a 13-bit
imaginary component YIm both in the two's complement
format. The output data is burst out from the core when the
transform has been performed to the stage that allows the
result to be output and the output port is enabled. The result
from the core is also in the normal order, i.e., Y(0) first,
followed by Y(1), Y(2) and so on.
The transform is scheduled to complete in four passes. In each
pass the controller fetches the intermediate data from the
internal dual port memory, sends it to the processing unit,
fetches the computation results from the processing unit and
writes the result back to memory for the next pass or for the
output. The CS2411 employs a Cooley-Tukey radix-4
decimation-in-frequency (DIF) to compute the FFT/IFFT. This
algorithm requires the calculation of radix-4 butterflies and
twiddle multiplications in multiple passes. Theoretically the
intermediate result value of a radix-4 butterfly with twiddle
operation may grow by a factor of up to 5.657. This represents
up to three-bit wordlength growth. In the last pass radix-16
operations are effectively performed. This will possibly result
in additional one bit wordlength growth. The core performs
one bit right-shift on the intermediate result unconditionally
4
The transform data is represented by complex numbers
SDC
CS2411
CLK
RST
CLR
IFFT
INPUT AND OUTPUT DATA FORMAT
TRANSFORM COMPUTATION
1024 Point FFT/IFFT
in the four passes. A rounding technique is employed to
achieve the maximal computation accuracy possible. When
the intermediate value is derived from the twiddle
multiplication result, or the input to the butterfly is scaled
down, round-to-the-nearest operation is performed. This
gives the maximal computation accuracy possible for the
given wordlength.
The CS2411 core performs scaling down operation by right
shifting the intermediate result in the four passes, according to
the scaling down control programmed. Table 5 lists the
relationship between the programming input signal SDC and
the number of scaling down bits performed in the four passes.
It is noted that there is no overflow in the computation when
the total number of shifting bits is equal to 11 bits.
FIXED WORD LENGTH AND ACCURACY
The CS2411 core uses fixed-point arithmetic to perform the
transform. The twiddle factors (Sine and Cosine values),
which are generated by the core internally, have 13-bit
accuracy. At the end of each computation pass, the result is
rounded to 13 bits. Figure 4 illustrates the word lengths at
various computation stages in the CS2411 core.
The rounding technique is employed to achieve the maximal
computation accuracy possible for the given word lengths.
When the intermediate value is derived from the twiddle
multiplication result, the output from the butterflies is scaled
down, or the intermediate result is right shifted, the core
performs the round-to-the-nearest operation to keep the loss
of accuracy minimal.
1024-point
Transform
SDC
Table 5: Number of Right Shifting Bits in Each Pass
000
001
010
011
100
101
110
111
Size
Table 4: Transform Operations in Each Pass
Pass 1 Pass 2 Pass 3 Pass 4
Radix-4
1
2
2
2
3
3
3
3
Pass 1
1
1
2
2
2
2
2
2
Radix-4
Pass 2
1
1
1
1
2
2
2
2
Radix-4
Pass 3
1
1
1
1
1
2
3
4
Radix-16
Pass 4
Total
10
11
4
5
6
7
8
9