M25PX80 Numonyx, M25PX80 Datasheet - Page 33

• Manufacturer Part Number: M25PX80
• Description: 8-mbit, Dual I/o, 4-kbyte Subsector Erase, Serial Flash Memory With 75 Mhz Spi Bus Interface
• Manufacturer: Numonyx

If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Figure 17. Page Program (PP) instruction sequence
1. Address bits A23 to A22 are Don’t care.
S
C
DQ0
S
C
DQ0
MSB
7
40
PP
6
41
) is initiated. While the Page Program cycle is in progress, the Status Register
0
5
42
Data byte 2
1
4
43 44 45 46 47 48 49 50
2
Instruction
3
3
2
4
Table 3
1
5
0
6
MSB
7
and
7
MSB
6
23
8
Table
5
22 21
Data byte 3
9 10
4
24-bit address
51
4) is not executed.
3
52 53 54 55
2
3
28 29 30 31 32 33 34 35
1
2
0
1
0
MSB
MSB
7
7
6
6
Data byte 256
5
5
Data byte 1
4
4
Table 17: AC
3
3
36 37 38
2
2
1
1
0
0
39
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