M25PX80 Numonyx, M25PX80 Datasheet - Page 13

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M25PX80

Manufacturer Part Number
M25PX80
Description
8-mbit, Dual I/o, 4-kbyte Subsector Erase, Serial Flash Memory With 75 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet

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4.5
4.6
4.7
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to I
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
device remains in this mode until another specific instruction (the Release from Deep
Power-down (RDP) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the Status Register bits.
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
CC1
.
Deep Power-down
(DP)), this can be used as an extra software protection
Section 6.4: Read Status Register (RDSR)
CC2
. The
for a
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