CAT25020 Catalyst Semiconductor, CAT25020 Datasheet - Page 9

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CAT25020

Manufacturer Part Number
CAT25020
Description
2k Spi Serial Cmos Eeprom
Manufacturer
Catalyst Semiconductor
Datasheet

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READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by a 8-bit address (for the
CAT25040, bit 3 of the read instruction opcode
contains A8 address bit).
After
CAT25010/20/40 will respond by shifting out data on
the SO pin (as shown in Figure 8). Sequentially stored
data can be read out by simply continuing to run the
clock. The internal address pointer is automatically
incremented to the next higher address as data is
shifted out. After reaching the highest memory
address, the address counter “rolls over” to the lowest
memory address, and the read cycle can be continued
indefinitely. The read operation is terminated by taking
CS
Figure 8. READ Timing
Notes:
Dashed Line = mode (1, 1) - - - - - -
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 9. RDSR Timing
Note: Dashed Line = mode (1, 1) - - - - - -
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
¯¯ high.
SCK
SCK
CS
SO
SI
CS
SO
SI
receiving
0
0
0
0
0
1
the
0
2
0
1
0
3
last
OPCODE
HIGH IMPEDANCE
OPCODE
0
X*
2
4
0
address
HIGH IMPEDANCE
0
5
3
1
6
0
1
4
7
A 7
bit,
8
1
5
9
the
BYTE ADDRESS
6
0
9
12
1
7
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25010/20/40 will shift out the
contents of the status register on the SO pin
(Figure 9). The status register may be read at any
time, including during an internal write cycle.
MSB
13
8
7
14
15
9
6
A 0
16
MSB
CAT25010, CAT25020, CAT25040
10
D7 D6 D5 D4 D3 D2 D1 D0
5
17
11
18 19
4
DATA OUT
DATA OUT
12
3
20
13
2
21
22
14
Doc. No. MD-1006 Rev. T
1
0

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