CAT25020 Catalyst Semiconductor, CAT25020 Datasheet - Page 5

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CAT25020

Manufacturer Part Number
CAT25020
Description
2k Spi Serial Cmos Eeprom
Manufacturer
Catalyst Semiconductor
Datasheet

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STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The RDY
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
Table 2. Status Register
Table 3. Block Protection Bits
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
¯¯¯¯ (Ready) bit indicates whether the device is
7
1
BP1
Status Register Bits
0
0
1
1
6
1
BP0
0
1
0
1
5
1
Array Address Protected
None
CAT25010: 060-07F
CAT25020: 0C0-0FF
CAT25040: 180-1FF
CAT25010: 040-07F
CAT25020: 080-0FF
CAT25040: 100-1FF
CAT25010: 000-07F
CAT25020: 000-0FF
CAT25040: 000-1FF
4
1
5
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
BP1
3
CAT25010, CAT25020, CAT25040
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
BP0
2
WEL
1
Doc. No. MD-1006 Rev. T
¯¯¯¯
RDY
0

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