AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 4
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AMD-762
Manufacturer Part Number
AMD-762
Description
System Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AMD-762.pdf
(122 pages)
- Current page: 4 of 122
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AMD-762™ System Controller Data Sheet
3
4
iv
Test
Electrical Data
2.4
2.5
2.6
3.1
3.2
3.3
3.4
4.1
4.2
4.3
4.4
4.5
Accelerated Graphics Port (AGP)
System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6.1 Full-On (C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.2 Halt (C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.3 Throttling with STPCLK# Assertion . . . . . . . . . . . . . . . 27
2.6.4 Power-On Suspend (S1) . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6.5 Suspend to RAM (S3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Board (Three-State) Test Mode
3.1.1 Board Test Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . 36
NAND Tree Test Mode
PLL Bypass Test Mode
Clock Output Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute Ratings
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3.1 Voltage Sequencing Requirements . . . . . . . . . . . . . . . 50
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Switching Characteristics and Requirements . . . . . . . . . . . . 53
4.5.1 Clock Switching Requirements . . . . . . . . . . . . . . . . . . . 53
4.5.2 DDR Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 56
66-MHz PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
33-MHz PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
S1 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
S3 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Preliminary Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
. . . . . . . . . . . . . . . . . . . . . . . 35
. . . . . . . . . . . . . . . . . . . . . 19
24416C—December 2001
Table of Contents
35
47
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