AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 28

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
2.3.1
2.3.2
Legacy Mode— Single
PCI Bus Southbridge
16
Memory Coherency
PCI Arbitration
The AMD-762 system controller assures that all data accesses
remain coherent:
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The AMD-762 system controller contains arbitration logic that
allocates ownership of the PCI bus among itself on behalf of
the processors, the Southbridge, and other PCI initiators.
Th e AMD-762 su p p o r t s u p to seve n b u s grant pins and a
dedicated grant pin for the Southbridge when opera t ing in
legacy mode. The request/grant pairs used depend on the
system configuration supported as described in the following
sections.
The legacy mode implies a standa rd system configu ra t ion
where the PCI bus typically operates at 33 MHz with a common
Southbridge such as the AMD-766 peripheral bus controller.
All PCI agents connect to this PCI bus segme n t and t h e ir
request grant pairs a re connected to the AMD-762 system
c o n t r ol l e r ’s REQ[6:0] # a n d GNT[6:0] # p i n s , w h i l e t h e
Southbridge connects to the SBREQ#/SBGNT# pins.
The SBREQ#/SBGNT# pins are treated differently than the
standard request/grant pairs as is required for legacy ISA DMA
cycles. To avoid potential deadlock conditions, the AMD-762
syst em controlle r a llows the SBREQ# to be assert ed for
extended periods of time. Bus masters using the REQ[6:0]# and
GNT[6:0]# signals are preempted when another requestor
All PCI/AGP accesses not in the GART range generate
processor probes assuring that reads receive only the latest
version of the data and that writes update only the latest
version of the data. Writes are always performed in order.
The GART range is by definition not cacheable. As a result,
all PCI/AGP accesses that are in the GART range are
subject to non-cacheable ordering rules—that is, they do not
generate probes to the processor, writes are performed in
order, and reads receive the results of all earlier writes.
Processor accesses to addresses mapped by the GART range
can either use the GART for the final address translation or
map the addresses through its page tables as a non-
cacheable memory type.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2