AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 34

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
2.5
66-MHz PCI Bus
22
System Clocking
n There are no ordering restrictions between AGP and PCI
n PCI transactions on the AGP bus follow the PCI ordering rules
n High-priority requests are re-ordered in front of low-priority
n There is no ordering relationship between high-priority
I f a l ow-p r i o r i t y d a t a t r a n s f e r i s i n p r og r e s s w h e n a
high-priority request is received, the data transfer completes
before the high-priority request is serviced —that is, a request
is not preem p t ab le . A high-priority re quest supersedes a
low-priority request on a request boundary only.
The AMD-762 system controller requires the following system
clocks:
n SYSCLK, used for clocking the AMD Athlon system busses
n AGPCLK, 66 MHz, used for clocking the AGP and PCI
n PCICLK, provides a 33-MHz PCI bus clock and is used to
There are two different clocking schemes for the PCI bus and
Southbridge as described in the following sections.
The highest performance option supports a 66-MHz primary
PCI bus on t he AMD-762 syst em controller , with a 33-MHz
secondary PCI bus controlled by an AMD-768 peripheral bus
controller’s PCI to PCI bridge. This mode also provides up to
two optional slots for 66-MHz peripherals.
transactions on the AGP bus.
described in the PCI Local Bus Specification, Revision 2.2.
requests.
reads, high-priority writes, and any other transfer type, such
as low-priority reads, low-priority writes, PCI reads, or PCI
writes.
and the DDR DRAM interface. This clock is typically either
100 MHz or 133 MHz. This clock is also used to create the
differential DDR DRAM clock outputs (CLKOUT[5:0],
CLKOUT[5:0]#).
internal logic. This feeds the PCI 66-MHz PLL in 66/33-MHz
PCI mode.
synchronize the PCI bus I/O signals to the 33-MHz PCI
signal domain when operating in 33-MHz-only PCI mode.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2