MBM29DL640E Fujitsu Microelectronics, Inc., MBM29DL640E Datasheet - Page 31

• Manufacturer Part Number: MBM29DL640E
• Description: Flash Memory 64 M 8 M X 8/4 M X 16 Bit Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

Extended Command
(1) Fast Mode
(2) Fast Programming
(3) CFI (Common Flash Memory Interface)
Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being
erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum
of “t
RY/BY output pin will be at Hi-Z and the DQ
use the address of the erasing sector for reading DQ
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode, except that the data must be read from
sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-
mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is
the same as programming in the regular Program mode, except that the data must be programmed to sectors
that are not erase-suspended. Reading successively from the erase-suspended sector while the device is in the
erase-suspend-program mode will cause DQ
detected by the RY/BY output pin, Data polling of DQ
regular Program operation. Note that DQ
any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
The device has a Fast Mode function. It dispenses with the initial two unclock cycles required in the standard
program command sequence by writing the Fast Mode command into the command register. In this mode, the
required bus cycle for programming consists of two bus cycles instead of four in standard program command.
Do not write erase command in this mode. The read operation is also executed after exiting from the fast mode.
To exit from this mode, it is necessary to write Fast Mode Reset command into the command register. The first
cycle must contain the bank address (see Figure 29) .The V
Fast Mode.
During Fast Mode, programming can be executed with two bus cycle operation. The Embedded Program Algo-
rithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (see Figure 29) .
The CFI (Common Flash Memory Interface) specification outlines device and the host system software interro-
gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible soft-
ware support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and data
from the memory cell can be read from the another bank. The higher order address (A
reading out the CFI Codes requires that the bank address (BA) be set at the write cycle. Following the command
write, a read cycle from specific address retrieves device information. Please note that output data of upper byte
(DQ
necessary to write the read/reset command sequence into the register.
SPD
15
to DQ
” to suspend the erase operation. When the device has entered the erase-suspended mode, the
8
) is “0” in word mode (16 bit) read. Refer to CFI code table (Table 12) . To terminate operation, it is
7
must be read from the Program address while DQ
7
2
bit will be at logic “1”, and DQ
to toggle. The end of the erase-suspended Program operation is
6
7
and DQ
or by the Toggle Bit I (DQ
2
to toggle (see the section on DQ
CC
active current is required even if CE
7
to determine if the erase operation has been
MBM29DL640E
6
will stop toggling. The user must
6
), which is the same as the
21
, A
2
20
).
6
, A
can be read from
19
) required for
V
80/90/12
IH
during
31