MBM29DL640E Fujitsu Microelectronics, Inc., MBM29DL640E Datasheet - Page 12

• Manufacturer Part Number: MBM29DL640E
• Description: Flash Memory 64 M 8 M X 8/4 M X 16 Bit Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

12
MBM29DL640E
(Continued)
*1: This command is valid during Fast Mode.
*2: This command is valid while RESET
*3: This command is valid during Hi-ROM mode.
*4: The data “00h” is also acceptable.
Notes : 1. Address bits A
Hi-ROM
Entry
Hi-ROM
Program *
Hi-ROM
Exit *
Command
Sequence
3
2. Bus operations are defined in Tables 2 and 3.
3. RA
4. RD
5. SPA
6. HRA
7. HRBA
8. The system should generate the following address patterns:
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
3
Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .
PA
SA Address of the sector to be erased. The combination of A
BA
PD
SD
(0, 0, 0, 1, 0) .
Word
Byte
Word
Byte
Word
Byte
Addresses are latched on the falling edge of the write pulse.
A
Address of the memory location to be programmed
Bank Address. Address setted by A
Sector group protection verify data. Output 01h at protected sector group addresses and output
Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
Address of the memory location to be read
00h at unprotected sector group addresses.
Data read from location RA during read operation.
12
Sector group address to be protected. Set sector group address and (A
Address of the Hi-ROM area Word Mode : 000000h to 00007Fh
Req’d
Write
will uniquely select any sector.
Bank Address of the Hi-ROM area (A
Word Mode : 555h or 2AAh to addresses A
Byte Mode : AAAh or 555h to addresses A
cles
Bus
Cy-
3
4
4
21
Write Cycle
AAAh
AAAh
AAAh
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
to A
555h
555h
555h
First Bus
11
80/90/12
X “H” or “L” for all address commands except or Program Address (PA) , Sector
AAh
AAh
AAh
Second Bus
Write Cycle
V
2AAh
2AAh
2AAh
555h
555h
555h
ID
.
55h
55h
55h
Byte Mode : 000000h to 0000FFh
21
, A
Write Cycle
AAAh
AAAh
AAAh
555h
555h
(HRBA)
555h
(HRBA)
20
Third Bus
21
, A
19
A
will select Bank A, Bank B, Bank C and Bank D.
20
10
A0h
88h
90h XXXh 00h
10
to A
to A
A
19
0
Fourth Bus
0
Read/Write
(HRA)
, and A
PA
—
V
21
Cycle
IL
, A
)
20
-1
, A
PD
—
19
, A
Write Cycle
18
Fifth Bus
—
—
—
, A
6
17
, A
, A
3
—
—
—
16
, A
, A
2
, A
15
Write Cycle
, A
Sixth Bus
1
—
—
—
, A
14
0
, A
)
13
—
—
—
and