OM6213 NXP Semiconductors, OM6213 Datasheet - Page 6

• Manufacturer Part Number: OM6213
• Description: Om6213 48 X 84 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.7
In the application, T4, T5 and T7 must be connected to
V
7.8
Data line and HV-gen programming input.
7.9
Input for the clock signal. 0 to 4.0 Mbits/s.
7.10
Input to select either command/address or data input.
7.11
The enable pin allows data to be clocked in; this signal is
active LOW.
7.12
If the on-chip oscillator is used, this input must be
connected to V
connected to pin OSC. If pin OSC is left at V
internal clock is disabled, the device is not clocked and the
display may be left in a DC state. To avoid this, it is
advisable to enter the Power-down mode before stopping
the clock.
7.13
This signal will reset the device and must be applied to
properly initialize the chip; this signal is active LOW.
8
8.1
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
clock signal is used, it must be connected to pin OSC.
8.2
The address counter assigns addresses to the display
data RAM for writing. The X address X[6:0] and the
Y address Y[2:0] are set separately. After a write operation
the address counter is automatically incremented by 1
according to the V flag.
2001 Nov 07
SS
48
. T1, T2, T3 and T6 must be left open-circuit.
BLOCK DIAGRAM FUNCTIONS
T1 to T7: test pads
SDIN: serial data line
SCLK: serial clock line
D/C: mode select
SCE: chip enable
OSC: oscillator
RES: reset
Oscillator
Address counter (AC)
84 pixels matrix LCD driver
DD1
. If an external clock is used, it must be
DD1
. If an external
SS1
, the
6
8.3
The OM6213 contains a 48
stores the display data. The RAM is divided into 6 banks of
84 bytes (6
transferred to the RAM via the serial interface. There is a
direct correspondence between the X address and the
column output number.
8.4
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
8.5
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits D and E in the command ‘Display
control’ (see Table 2).
8.6
The OM6213 contains 48 rows and 84 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 2 shows typical waveforms. Unused
outputs should be left unconnected.
8.7
The voltage multiplier (i.e. charge pump) generates the
V
programmable (default value 4).
LCD
voltage. The multiplication factor is Module Maker
Display Data RAM (DDRAM)
Timing generator
Display address counter
LCD row and column drivers
V
LCD
generator
8
84 bits). During RAM access, data is
84 bit static RAM which
Product specification
OM6213