ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 26

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also
REFCLKP, REFCLKN, if using a high frequency reference clock,
such as 155 MHz). It is also necessary for the PIN/NIN input
traces to be matched in length, and the CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN output traces to be matched
in length to avoid skew between the differential traces.
All high speed CML outputs (CLKOUTP, CLKOUTN, DATAOUTP,
and DATAOUTN) require 100 Ω back termination chip resis-
tors connected between the output pin and VCC. Place these
resistors as close as possible to the output pins. These 100 Ω
resistors are in parallel with on-chip 100 Ω termination resistors
to create a 50 Ω back termination (see Figure 36).
The high speed inputs (PIN and NIN) are internally terminated
with 50 Ω to an internal reference voltage (see Figure 37).
A 0.1 μF capacitor is recommended between VREF, Pin 3, and
GND to provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width. Center the land on the pad to ensure that the solder joint
size is maximized. The bottom of the lead frame chip scale
VCC
ADN2817/ADN2818
Figure 37. ADN2817/ADN2818 AC-Coupled Input Configuration
Figure 36. Typical ADN2817/ADN2818 Applications Circuit
TIA
TIA
100Ω
VCC
100Ω
50Ω
0.1µF
100Ω
C
C
IN
IN
VCC
100Ω
PIN
NIN
VREF
ADN2817/ADN2818
50Ω
0.1µF
0.1µF
50Ω
50Ω
3kΩ
V
V
TERM
TERM
50Ω
50Ω
2.5V
Rev. 0 | Page 26 of 36
package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
to prevent solder from leaking through the vias during reflow.
This ensures a solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2817/ADN2818 must
be chosen such that the device works properly over the full
range of data rates used in the application. When choosing the
capacitors, the time constant formed with the two 50 Ω resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can droop due to baseline wander (see Figure 38),
causing pattern dependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection may
require some trade-offs between droop and PDJ.
For example, assuming that 2% droop can be tolerated, the
maximum differential droop is 4%. Normalizing to V
where:
τ is the RC time constant (C is the ac coupling capacitor,
R = 100 Ω seen by C).
t is the total discharge time, which is equal to n
n is the number of CIDs.
T is the bit period.
Calculate the capacitor value by combining the equations
for τ and t
Once the capacitor value is selected, the PDJ can be
approximated as
where:
PDJ
<0.01 UI p-p typical.
t
where BW ~ 0.7 (bit rate).
Note that this expression for t
The output rise time for the ADN2817/ADN2818 is ~100 ps
regardless of data rate.
r
is the rise time, which is equal to 0.22/BW,
ps p-p
Droop = Δ V = 0.04 V = 0.5 V
C = 12nT/R
PDJ
is the amount of pattern dependent jitter allowed;
ps p-p
= 0.5t
r
(
1
−
e
(
−
nT/RC
r
)
is accurate only for the inputs.
)
0 /
p-p
6 .
(1 − e
–t/τ
) ; therefore, τ = 12t
Τ
.
p-p