ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 21

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
I
The ADN2817/ADN2818 supports a 2-wire, I
serial bus driving multiple peripherals. Two inputs, serial data
(SDA) and serial clock (SCK), carry information between any
devices connected to the bus. Each slave device is recognized by
a unique address. The ADN2817/ADN2818 have two possible
7-bit slave addresses for both read and write operations. The
MSB of the 7-bit slave address is factory programmed to 1. Bit 5
of the slave address is set by Pin 19, SADDR5. Slave Address
Bits[4:0] are defaulted to all 0s. The slave address consists of the
7 MSBs of an 8-bit word. The LSB of the word sets either a read
or write operation (see Figure 18). Logic 1 corresponds to a read
operation and Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establishing
a start condition, defined by a high to low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/ W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines waiting for
the start condition and correct transmitted address. The R/ W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADN2817/ADN2818 act as standard slave devices on the
bus. The data on the SDA pin is eight bits long supporting the
7-bit addresses plus the R/ W bit. The ADN2817/ADN2818 have
eight subaddresses to enable the user-accessible internal
registers (see
the first byte as the device address and the second byte as the
starting subaddress. Auto-increment mode is supported,
allowing data to be read from, or written to, the starting
subaddress and each subsequent address without manually
addressing the subsequent subaddress. A data transfer is always
terminated by a stop condition. The user can also access any
unique subaddress register on a one-by-one basis without
updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2817/ADN2818
do not issue an acknowledge and return to the idle condition. If
2
C INTERFACE
Table 1
through
Table 7
). It, therefore, interprets
2
C-compatible
Rev. 0 | Page 21 of 36
the user exceeds the highest subaddress while reading back in
auto-increment mode, then the highest subaddress register con-
tents continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. In a no acknowledge
condition, the SDATA line is not pulled low on the ninth pulse.
See Figure 19 and Figure 20 for sample read and write data
transfers and Figure 21 for a more detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2817/ADN2818. However, support for
an optional reference clock is provided. The reference clock can
be driven differentially or single-ended. If the reference clock is not
used, tie REFCLKP to VCC, and either leave REFCLKN floating or
tie it to VEE (the inputs are internally terminated to VCC/2). See
Figure 32 through Figure 34 for sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical
and 100 ppm accuracy is sufficient.
OSC OUT
VCC
CLK
Figure 33. Single-Ended REFCLK Configuration
Figure 32. Differential REFCLK Configuration
REFCLKN
REFCLKP
REFCLKN
REFCLKP
10
11
10
11
100kΩ
100kΩ
ADN2817/ADN2818
ADN2817/ADN2818
ADN2817/ADN2818
100kΩ
100kΩ
BUFFER
BUFFER
VCC/2
VCC/2