ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 17

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The ADN2817/ADN2818 are delay- and phase-locked loop
circuits for clock recovery and data retiming from an NRZ
encoded data stream. The phase of the input data signal is
tracked by two separate feedback loops that share a common
control voltage. A high speed delay-locked loop path uses a
voltage controlled phase shifter to track the high frequency
components of input jitter. A separate phase control loop,
comprised of the VCO, tracks the low frequency components of
input jitter. The initial frequency of the VCO is set by yet a third
loop, which compares the VCO frequency with the input data
frequency and sets the coarse tuning voltage. The jitter tracking
phase-locked loop controls the VCO by the fine-tuning control.
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to higher frequency
and increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while, simultaneously, the
delayed data loses phase. Because the loop filter is an integrator,
the static phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 28 shows that
the jitter transfer function, Z(s)/X(s), is second-order low-pass,
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 29). This makes this circuit ideal for signal regene-
rator applications, where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
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The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors, so the phase shifter remains close to the center of
its range and thus contributes little to the low frequency jitter
accommodation.
INPUT
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
DATA
Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL
X(s)
Figure 28. ADN2817/ADN2818 PLL/DLL Architecture
RECOVERED
CLOCK
Z(s)
n psh
e(s)
o
psh
FREQUENCY (kHz)
JITTER TRANSFER FUNCTION
Z(s)
X(s)
TRACKING ERROR TRANSFER FUNCTION
X(s)
e(s)
=
=
d/sc
s
s
d psh
2
2
ADN2817/ADN2818
cn
do
+
c
JITTER PEAKING
IN ORDINARY PLL
s
d psh
1/n
+
s
s
c
2
1
n psh
o
+
o/s
do
cn
+ 1
ADN28xx
Z(s)
X(s)