ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 20

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
HARMONIC DETECTOR
The ADN2817/ADN2818 provide a harmonic detector, which
detects whether the input data has changed to a lower harmonic
of the data rate onto which the VCO is currently locked. For
example, if the input data instantaneously changes from OC-48,
2.488 Gbps, to an OC-12, 622.080 Mbps bit stream, this could
be perceived as a valid OC-48 bit stream, because the OC-12
data pattern is exactly 4× slower than the OC-48 pattern.
Therefore, if the change in data rate is instantaneous, a 101
pattern at OC-12 is perceived by the ADN2817/ADN2818 as
a 111100001111 pattern at OC-48. If the change to a lower
harmonic is instantaneous, a typical CDR could remain locked
at the higher data rate.
The ADN2817/ADN2818 implement a harmonic detector that
automatically identifies whether the input data has switched to
a lower harmonic of the data rate onto which the VCO is
currently locked. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2817/ADN2818 automatically lock onto the new data rate,
and the LOL pin is deasserted.
However, the harmonic detector does not detect higher har-
monics of the data rate. If the input data rate switches to a
higher harmonic of the data rate onto which the VCO is
currently locked, the VCO loses lock, the LOL pin is asserted,
and a new frequency acquisition is initiated. The ADN2817/
ADN2818 automatically lock onto the new data rate.
The time to detect lock to harmonic is
where:
1/T
switched from OC-48 to OC-12, then T
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS or 8b/10b encoding.
When the ADN2817/ADN2818 is placed in lock to reference
mode, the harmonic detector is disabled.
LIMITING AMPLIFIER (ADN2817 ONLY)
The limiting amplifier on the ADN2817 has differential inputs
(PIN/NIN) that internally terminate with 50 Ω to an on-chip
voltage reference (VREF = 2.5 V typically). The inputs are
typically ac-coupled externally, although dc coupling is possible
as long as the input common-mode voltage remains above 2.5 V
(see Figure 39, Figure 40, and Figure 41). Input offset is factory
trimmed to achieve better than 6 mV typical sensitivity with
minimal drift. The limiting amplifier can be driven
differentially or single-ended.
SLICE LEVEL ADJUST (ADN2817 ONLY)
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/SLICEN inputs. If no adjustment of
d
16,384 × (T
is the new data rate. For example, if the data rate is
d
/ρ)
d
= 1/622 MHz.
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the slice level is needed, SLICEP/SLICEN should be tied to
VEE. The gain of the slice adjustment is ~0.1 V/V.
LOSS OF SIGNAL (LOS) DETECTOR
(ADN2817 ONLY)
The receiver front end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point vs. resistor
value is illustrated in Figure 6. If the input level to the ADN2817
drops below the programmed LOS threshold, the output of the
LOS detector, LOS Pin 22, is asserted to a Logic 1. The LOS
detector response time is 450 ns by design, but is dominated by
the RC time constant in ac-coupled applications. The LOS pin
defaults to active high. However, by setting Bit CTRLC[2] to 1,
the LOS pin is configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means
that, if the input level drops below the programmed LOS
threshold causing the LOS pin to assert, the LOS pin is not
deasserted until the input level has increased to 6 dB (2×) above
the LOS threshold (see Figure 31).
The LOS detector and the slice level adjust can be used simul-
taneously on the ADN2817. This means that any offset added to
the input signal by the slice adjust pins does not affect the LOS
detector measurement of the absolute input level.
SQUELCH MODE
Two squelch modes are available with the ADN2817/ADN2818:
squelch DATAOUT and CLKOUT mode, and squelch
DATAOUT or CLKOUT mode.
Squelch DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the squelch
input, Pin 27, is driven to a TTL high state, both the clock and
data outputs are set to the zero state to suppress downstream
processing. If the squelch function is not required, Pin 27
should be tied to VEE.
Squelch DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
Figure 31. ADN2817 LOS Detector Hysteresis
LOS OUTPUT
HYSTERESIS
LOS THRESHOLD
INPUT LEVEL
t