ST92195C STMicroelectronics, ST92195C Datasheet - Page 186

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

I
7.10.3 Functional Description
Refer to
Figure 2
By default, the I
mode, except when it initiates a transmit or receive
sequence.
After the microcontroller power-on reset state, the
I
(I2CCTR register) is reset.
7.10.3.1 Configuring the interface
Before using the I
lows.
If it is to be used in slave mode, write the address
assigned to the interface in the I2COAR register.
If it is to be used in master mode, write the SCL
clock frequency in the I2CFQR register.
Figure 105. I²C interface block diagram
2
2
C BUS INTERFACE (Cont’d)
C interface is in reset state until the CLEAR bit
SDA 1
SDA 2
SCL 1
SCL 2
Section 0.1.6
gives the block diagram of the cell.
2
C interface is in inactive slave
2
C interface, configure it as fol-
for the bit definitions.
SDA In
SCL In
GENERATION
CLOCK
SDA Out
UNIT
START & STOP
DETECTION
STATUS REGISTER 2 (I2CSTR2)
ST92195C/D - TWO-CHANNEL I
UNIT
STATE MACHINE
INTERRUPT
BIT TRANSFER
ARBITRATION
Then, select one of the two buses available and
configure the corresponding pins to the alternate
function (refer to the I/O port chapter).
Depending on your application, you may use the
advanced features (see the UNPROC and UNEXP
bits of the I2CSTR2 register) by setting the AFEN
bit of the I2CCTR register.
You may also optionally set the RSRT and STOP
bits of the I2CCTR register.
You can enable the interrupt on stop condition and
the Spike filter by setting the ISCEN and SFEN
bits of the I2CSTR1 register.
If you want to use the monitor feature, then set the
MONITOR bit in the I2CCTR register.
In all cases reset the CLEAR bit of the I2CCTR
register to enable the I
ERROR AND
COMPARATOR
UNIT
SHIFT DATA
REGISTER
ADDRESS
UNIT
START & STOP
GENERATION
UNIT
Fast Mode Enable
OWN ADDRESS REGISTER (I2COAR)
Acknowledge Bit
2
FREQUENCY REGISTER (I2CFQR)
C BUS INTERFACE (I2C)
STATUS REGISTER 1 (I2CSTR1)
CONTROL REGISTER (I2CCTR)
2
DATA REGISTER (I2CDR)
C interface.
CPU Interrupt
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