ST92195C STMicroelectronics, ST92195C Datasheet - Page 176

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 95. SPI I/O Pins
n
LATCH
LATCH
LATCH
PORT
PORT
PORT
BIT
BIT
BIT
INT2
SDO
SCK
SDI
SPI
ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI)
INT2
SDI
SCK
SDO
7.9.4 Interrupt Structure
The SPI peripheral is associated with external in-
terrupt channel B0 (pin INT2). Multiplexing be-
tween the external pin and the SPI internal source
is controlled by the SPEN and BMS bits, as shown
in
The two possible SPI interrupt sources are:
– End of transmission (after each byte).
– S-bus/I
Care should be taken when toggling the SPEN
and/or BMS bits from the “0,0” condition.
changing the interrupt source from the external pin
to the internal function, the B0 interrupt channel
should be masked. EIMR.2 (External Interrupt
Mask Register, bit 2, IMBO) and EIPR.2 (External
Interrupt Pending Register bit 2, IMP0) should be
“0” before changing the source. This sequence of
events is to avoid the generating and reading of
spurious interrupts.
A delay instruction lasting at least 4 clock cycles
(e.g. 2 NOPs) should be inserted between the
SPEN toggle instruction and the Interrupt Pending
bit reset instruction.
The INT2 input Function is always mapped togeth-
er with the SCK input Function, to allow Start/Stop
bit detection when using S-bus/I
A start condition occurs when SDI goes from “1” to
“0” and SCK is “1”. The Stop condition occurs
when SDI goes from “0” to “1” and SCK is “1”. For
both Stop and Start conditions, SPEN = “0” and
BMS = “1”.
Table 31. Interrupt Configuration
SPEN
Table 31 Interrupt
0
0
1
BMS
2
C-bus start or stop condition.
X
0
1
External channel INT2
S-bus/I
End of a byte transmission
Configuration.
2
C bus start or stop condition
Interrupt Source
2
C-bus protocols.
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