S5K3A1EA Samsung Semiconductor, Inc., S5K3A1EA Datasheet - Page 13

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S5K3A1EA

Manufacturer Part Number
S5K3A1EA
Description
1/3?sxga Cmos Image Sensor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1/3 INCH SXGA CMOS IMAGE SENSOR
PIN DESCRIPTION
VDDD (6,25,48)
VDDIO (5)
VSSD (19,26,47)
VSSIO (20)
VDDA(1,4,21,24,
28,29,37,44,45)
VSSA(2,3,22,23,
27,30,36,43,46)
MCLK (7)
RSTN (40)
STBYN (39)
STRB (38)
DATA0~DATA9
(8 ~ 17)
DCLK (18)
HSYNC (32)
VSYNC (31)
SCL (41)
SDA (42)
VREF (35)
TEST1 (33)
TEST2 (34)
Pin No
Power
Power
Power
Power
Power
Power
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Digital power supply
Analog power supply
Master clock
Reset
Standby
Strobe
Image data output
Data clock
Horizontal sync clock
Vertical sync clock
Serial interface clock
Serial interface data
Reference voltage
Test input 1
Test input 2
Name
For logical circuit (V
For I/O circuit (V
0V (GND)
0V (GND)
For analog circuit (V
0V (GND)
Master clock pulse input for all timing generators.
Initializing all the device registers. (Active low)
Activating power saving mode.
Triggering the integration start and stop when single
frame capture mode.
10-bit image data outputs. When ADC resolution is
reduced, the unused lower bits are set to 0.
Image data output synchronizing pulse output.
Horizontal synchronizing pulse or data valid signal
output.
Vertical synchronizing pulse or line valid signal output.
I2C serial interface clock input
I2C serial interface data bus
(external pull-up resistor required)
For proper operation, the external capacitor larger than
0.1uF must be connected between VREF and VDDA.
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
( high=normal operation, low=power saving mode )
DDL
DDL
)
DDH
)
Function
)
S5K3A1EA
13

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