S5K3A1EA Samsung Semiconductor, Inc., S5K3A1EA Datasheet
S5K3A1EA
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S5K3A1EA Summary of contents
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... INCH SXGA CMOS IMAGE SENSOR (1/3” SXGA CMOS Image Sensor) Preliminary Specification S5K3A1EA Revision 0.4 Jun, 2004 S5K3A1EA 1 ...
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... Revision No. History 0.0 Initial Draft 0.1 DC Characteristics Changed. 0.2 Register Map Updated. 0.3 Imaging Characteristics Changed 0.4 Imaging Characteristics Changed S5K3A1EA13 Product Added AC Characteristics Changed Ob_area Recommended Setting Changed 2 1/3” SXGA CMOS IMAGE SENSOR Draft Date Remark Feb.03, 2004 Preliminary Mar.29.2004 Apr.09.2004 Jun.10.2004 ...
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... INCH SXGA CMOS IMAGE SENSOR INTRODUCTION The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG 0.18um CMOS image sensor process technology developed for image application to realize high efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically ...
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... S5K3A1EA BLOCK DIAGRAM Main Clock MCLK Divider RSTN STBYN STRB Timing Generator VSYNC HSYNC DCLK Control Registers SCL Interface SDA 4 1/3” SXGA CMOS IMAGE SENSOR 10-bit Column ADC Odd Column CDS Active Pixel Sensor Array Even Column CDS 10-bit Column ADC ...
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... Optical Active Pixels Black Pixels S5K3A1EA 5 ...
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... S5K3A1EA PIN CONFIGURATION MCLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DCLK First Readout Pixel 17 18 1/3” SXGA CMOS IMAGE SENSOR 42 SDA 41 SCL 40 RSTN 39 STBYN 38 STRB 37 VDDA 36 VSSA 35 VREF 34 TEST2 33 TEST1 32 HSYNC 31 VSYNC ...
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... Digital and I/O maximum absolute voltage (VDDIO supply relative to VSSIO VDDD supply relative to VSSD) Input voltage Operating temperature Storage temperature NOTES: 1. The maximum allowed storage temperature for S5K3A1EA01. 2. The maximum allowed storage temperature for S5K3A1EA02 and S5K3A1EA03. Symbol Value V -0.3 to 3.8 DDH V -0.3 to 2.7 DDL V -0 ...
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... S5K3A1EA ELECTRICAL CHARACTERISTICS DC Characteristics (T = -20 to +60qC 15pF Characteristics Symbol V Operating voltage DDH V DDL (1) V Input voltage Input leakage IL (2) current I Input leakage current ILD (3) with pull-down V High level output OH (4) voltage Low level output V OL (5) voltage High-Z output leakage ...
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... INCH SXGA CMOS IMAGE SENSOR S5K3A1EA 9 ...
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... S5K3A1EA Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values 25qC if not specified.) A Characteristic (1) Saturation level (2) Sensitivity (3) Dark level ...
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... HSYNC output PDMH t DCLK output PDMD t DATA output PDMO t VSYNC output PDDV t HSYNC output PDDH t DATA output PDDO t RSTN=low(active) WRST t STBYN=low(active) WSTB t PDMD = 10pF) L Min Typ Max PDDH t PDMH S5K3A1EA Unit MHz ns (1) T MCLK 11 ...
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... S5K3A1EA MCLK t WRST RSTN STBYN system reset Serial Interface Characteristics Characteristic Symbol Clock frequency Clock high pulse width Clock low pulse width Clock rise/fall time Data set-up time Data hold time START condition setup time START condition hold time STOP condition setup time ...
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... VREF and VDDA. Test input signal. Though it can be opened in normal operation (internally pulled down recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down recommended to ground the test pins. S5K3A1EA Function ) DDL ) DDL ) ...
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... S5K3A1EA CONTROL REGISTERS Address Reset Bits (Hex) Value 00h 01h [7] [6] [5] [4:2] [1] [0] 01h 00h [7] [6] [5] [4] [3:2] [1:0] 02h 00h [2:0] 03h 0Eh [7:0] 04h 00h [2:0] 05h 0Eh [7:0] 06h 04h [2:0] 07h 00h [7:0] 08h 05h [2:0] 09h 00h [7:0] 0Ah 80h [7:0] 14 Mnemonic (Factory use only) CDS timing control ...
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... VSYNC width vswd[7: (default) vsstrt_high VSYNC start position vsstrt[9: (default) vsstrt_low Vertical blank depth vblank_high vblank[12:0] = 101d (default) vblank_low hswd HSYNC width hswd[7:0] = 32d (default) hsstrt_high HSYNC start position hsstrt[9: (default) hsstrt_high hblank_high Horizontal blank depth hblank[15:0] = 142d (default) hblank_low S5K3A1EA Description 15 ...
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... S5K3A1EA Address Reset Bits (Hex) Value 1Ch 00h [6:0] 1Dh 00h [6:0] 1Eh 00h [6:0] 1Fh 00h [6:0] 20h 0Fh [4:0] 21h 0Fh [4:0] 22h 0Fh [4:0] 23h 0Fh [4:0] 24h 80h [7:0] 25h 80h [7:0] 26h 80h [7:0] 27h 80h [7:0] 28h 14h [7] [6:0] 29h 00h [7:0] 16 Mnemonic Red channel gain pgcr pgcr[6: (default) ...
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... Adlc mode works till adlc length value adlc_mod_a 0b: disabled (default), 1b: enabled Feedback gain value about ADLC feedback_gain_B 00b : 0, 10b : 0.75, ADLC formula : D D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1) Feedback gain value about ADLC feedback_gain_A 00b : 0, 10b : 0.25(default), S5K3A1EA Description 01b : 0.5(default), 11b : 1 = D(n) + adcoffs final 01b : 0.5, 11b : 0.125 17 ...
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... S5K3A1EA Address Reset Bits (Hex) Value 2Fh 00h [7] [6] [5] [4] [3] [2] [1:0] 30h 02h [7:6] [5] [4] [3] [2] [1] [0] 31h 1Eh [7:0] 32h 32h [7:0] 33h 00h [5:0] 34h 00h [7:0] 35h CCh [7:4] [3:0] 36h CCh [7:4] [3:0] 18 Mnemonic dckout_en DCK pad control 0b : output enable (default stable value I/O driver fan-out control register. ...
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... This register value is must larger than OB line. Not use (Factory use only)Add tg to reduce NIT. tx_add shutx_sel (Factory use only)Enlarge shutter TX width to reduce NIT. cal_en (Factory use only) calibration enable cal_stp (Factory use only) calibration signal control S5K3A1EA Description 19 ...
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... S5K3A1EA OPERATION DESCRIPTION 1. Output Data Format 1-1. Main Clock Divider All the data output and sync signals are synchronized to data clock output (DCLK generated by dividing the input main clock (MCLK). The dividing ratio 16, and 32 according to main clock dividing control register (mcdiv) ...
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... subsr=00b, subsc=10b adcres = 0 548 404 332 300 278 270 S5K3A1EA ...
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... S5K3A1EA In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when shutter control register (shutc) is set to “1”. In shutter operation, the integration time is determined by the Row Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc) In CFCM integration time control ...
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... Global Gain = (sgg[4:0]+ 112 128 0 Figure 3. Relative Channel Gain Program m able Gain Control S5K3A1EA 112 128 23 ...
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... S5K3A1EA The ADC gain is dependent on MCLK frequency (not on DCLK frequency) and ADC resolution. The default global gain is set for typical MCLK frequency (12MHz) and 10-bit ADC. When the frequency and ADC resolution is changed, the global gain should be changed to maintain the resulting gain over unity for assuring appropriate ADC conversion range ...
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... Hexadecimal - - - - - - - - - - - - S5K3A1EA 25 ...
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... S5K3A1EA appropriately programming these four register values, the different output resolution according to the signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curve as shown in Figure 6 ...
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... STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL contains a serial two-wire half duplex interface that 2 C bus interface is composed of S5K3A1EA 27 ...
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... S5K3A1EA SCL SDA “0” “0” “1” 2 Start I C Bus Address SCL SDA 7 6 Data to Write SCL SDA “0” “0” “1” “0” 2 Start I C Bus Address SCL SDA “0” “0” “1” ...
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... HSYNC (hsdisp=0) HSYNC (hsdisp=1) DATA 1 frame = wrd + vblank ( 1125 rows ) vswd (1row) wrp(14th row) wrd (1024 rows) 1 frame = wrd + vblank ( 1125 rows ) vsstrt vswd wrp(14th row) 2rows wrp(14th row) wrd (1024 rows) S5K3A1EA vblank (101 rows) 2rows vblank (101 rows) 29 ...
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... S5K3A1EA VERTICAL TIMING DIAGRAM (continued) ( Short OB Line & Fixed Vertical Sync mode) isp_sel = 1& fix_vs = 1 1 frame = wrd + vblank ( 1125 rows ) Normal frame output VSYNC vswd (1row) 4 rows = vsend_ofset HSYNC DATA wrp(14th row) ( Short OB Line & Normal Sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d XG ...
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... Integration time for 1st readout row Integration time for 2nd readout row Integration time for 3rd readout row Integration time for 4th readout row Integration time for all pixels Can be opened S5K3A1EA Normal frame output wrp(14th row) wrd (1024 rows) Normal frame output wrp(14th row) ...
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... S5K3A1EA ( Global Shutter Case, sfcen=1 & global_mod = 1 ) STRB Integration time for all pixels VSYNC HSYNC DATA 32 1/3” SXGA CMOS IMAGE SENSOR Normal frame output wrp(14th row) wrd (1024 rows) ...
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... Delayed Horizontal Sync Case ) VSYNC HSYNC hsstrt DCLK DATA ( Horizontal Data Valid Mode Case ) hsdisp=1 VSYNC HSYNC DCLK DATA 1 row = wcw + hblank ( 1422 columns ) wcw ( 1280 columns ) 1 row = wcw + hblank hswd wcw wcw S5K3A1EA hblank ( 142 columns ) hblank 33 ...
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... S5K3A1EA PACKAGE DIMENSION 48pin CLCC (unit = mm) 7 TOP VIEW 18 SIDE VIEW BOTTOM VIEW R 0.15 4 Corners 34 14.22SQ +0.30/-0. Glass 11.176 r 0.13 1.016 r 0. 0.51 r 0.08 1/3” SXGA CMOS IMAGE SENSOR 42 Center of Image Area (X=+0.088 r 0.15, Y=0.002r 0.15 from package center) Max. Chip Rotation = r1.5 degree Max ...