DSPIC30F3011 Microchip Technology Inc., DSPIC30F3011 Datasheet - Page 215

• Manufacturer Part Number: DSPIC30F3011
• Description: Dspic30f3010/3011 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
© 2007 Microchip Technology Inc.
CLKOUT and I/O....................................................... 174
External Clock........................................................... 169
I
I
Input Capture (CAPX) ............................................... 180
Motor Control PWM Module...................................... 182
Motor Control PWM Module Falult............................ 182
OC/PWM Module ...................................................... 181
Oscillator Start-up Timer ........................................... 175
Output Compare Module........................................... 180
Power-up Timer ........................................................ 175
QEI Module Index Pulse ........................................... 184
Reset......................................................................... 175
SPI Module
TimerQ (QEI Module) External Clock ....................... 179
Type 1, 2, 3, 4 and 5 Timer External Clock............... 177
Watchdog Timer........................................................ 175
Center Aligned PWM .................................................. 95
Dead-Time .................................................................. 97
Edge-Aligned PWM..................................................... 95
PWM Output ............................................................... 83
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy............... 172
A/D Conversion
Bandgap Start-up Time............................................. 176
Brown-out Reset ....................................................... 175
CLKOUT and I/O....................................................... 174
External Clock........................................................... 170
I
I
Input Capture ............................................................ 180
Motor Control PWM Module...................................... 182
Oscillator Start-up Timer ........................................... 175
Output Compare Module........................................... 180
Power-up Timer ........................................................ 175
QEI Module
Quadrature Decoder ................................................. 183
Reset......................................................................... 175
Simple OC/PWM Mode............................................. 181
SPI Module
Timer1 External Clock............................................... 177
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode)..................................... 191
C Bus Data (Slave Mode)....................................... 192
Master Mode ..................................................... 190
Slave Mode ....................................................... 192
Master Mode ..................................................... 190
Slave Mode ....................................................... 192
Master Mode (CKE = 0) .................................... 185
Master Mode (CKE = 1) .................................... 186
Slave Mode (CKE = 0) ...................................... 187
Slave Mode (CKE = 1) ...................................... 188
Not Tied to V
Not Tied to V
(MCLR Tied to V
10-Bit High-speed ............................................. 198
External Clock................................................... 179
Index Pulse ....................................................... 184
Master Mode (CKE = 0) .................................... 185
Master Mode (CKE = 1) .................................... 186
Slave Mode (CKE = 0) ...................................... 187
Slave Mode (CKE = 1) ...................................... 189
DD
DD
), Case 1 .................................. 142
), Case 2 .................................. 142
DD
).......................................... 142
Confidential
Timing Specifications
Trap Vectors ....................................................................... 44
U
UART
Unit ID Locations .............................................................. 135
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ......................................................... 135
Wake-up from Sleep and Idle ............................................. 45
Watchdog Timer
Watchdog Timer (WDT)............................................ 135, 145
WWW Address ................................................................. 215
WWW, On-Line Support ....................................................... 6
dsPIC30F3010/3011
Timer3 and Timer5 External Clock ........................... 178
Watchdog Timer ....................................................... 175
PLL Clock ................................................................. 171
Address Detect Mode ............................................... 119
Auto Baud Support ................................................... 120
Baud Rate Generator ............................................... 119
Enabling and Setting Up UART ................................ 117
Loopback Mode ........................................................ 119
Module Overview...................................................... 115
Operation During CPU Sleep and Idle Modes.......... 120
Receiving Data ......................................................... 118
Reception Error Handling ......................................... 118
Transmitting Data ..................................................... 117
UART1 Register Map ............................................... 121
UART2 Register Map ............................................... 121
Module (UART)......................................................... 115
Timing Characteristics .............................................. 175
Timing Requirements ............................................... 175
Enabling and Disabling............................................. 145
Operation.................................................................. 145
Alternate I/O ..................................................... 117
Disabling........................................................... 117
Enabling ........................................................... 117
Setting Up Data, Parity and Stop Bit Selections117
In 8-bit or 9-bit Data Mode................................ 118
Interrupt ............................................................ 118
Receive Buffer (UxRCB)................................... 118
Framing Error (FERR) ...................................... 119
Idle Status ........................................................ 119
Parity Error (PERR) .......................................... 119
Receive Break .................................................. 119
Receive Buffer Overrun Error (OERR Bit) ........ 118
In 8-bit Data Mode ............................................ 117
In 9-bit Data Mode ............................................ 117
Interrupt ............................................................ 118
Transmit Buffer (UxTXB) .................................. 117
DS70141D-page 213