DSPIC30F3011 Microchip Technology Inc., DSPIC30F3011 Datasheet - Page 132

• Manufacturer Part Number: DSPIC30F3011
• Description: Dspic30f3010/3011 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F3010/3011
19.8
The analog input model of the 10-bit ADC is shown in
Figure 19-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
ance combine to directly affect the time required to
charge the capacitor C
ance of the analog sources must therefore be small
enough to fully charge the holding capacitor within the
chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the A/D converter,
the maximum recommended source impedance, R
5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
FIGURE 19-3:
DS70141D-page 130
DD
IC
) and the internal sampling switch (R
and the holding capacitor charge time.
Note:
A/D Acquisition Requirements
C
PIN
Legend: C
VA
value depends on device package and is not tested. Effect of C
HOLD
Rs
S
ADC ANALOG INPUT MODEL
), the interconnect impedance
HOLD
V
I leakage
R
R
C
ANx
) must be allowed to fully
PIN
T
IC
SS
HOLD
C
. The combined imped-
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
V
SS
DD
) imped-
V
V
T
T
= 0.6V
= 0.6V
Confidential
S
, is
R
I leakage
± 500 nA
IC
≤ 250Ω
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
The user must allow at least 1 T
time, T
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
ADC. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Section 23.0 "Electrical Characteristics" for T
sample time requirements.
SAMP
Sampling
Switch
R
SS
, between conversions to allow each
PIN
negligible if Rs ≤ 5 kΩ.
R
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2007 Microchip Technology Inc.
AD
period of sampling
AD
and