DSPIC30F2012 Microchip Technology Inc., DSPIC30F2012 Datasheet - Page 197

• Manufacturer Part Number: DSPIC30F2012
• Description: Dspic30f2011/2012/3012/3013 High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Internal Clock Timing Examples ....................................... 158
Internet Address................................................................ 199
Interrupt Controller
Interrupt Priority .................................................................. 64
Interrupt Sequence ............................................................. 67
Interrupts ............................................................................. 63
L
Load Conditions ................................................................ 155
Low Voltage Detect (LVD) ................................................ 129
Low-Voltage Detect Characteristics .................................. 152
LVDL Characteristics ........................................................ 152
M
Memory Organization.......................................................... 27
Microchip Internet Web Site .............................................. 199
Modulo Addressing ............................................................. 42
MPLAB ASM30 Assembler, Linker, Librarian ................... 142
MPLAB ICD 2 In-Circuit Debugger ................................... 143
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment Software .. 141
MPLAB PM3 Device Programmer .................................... 143
MPLINK Object Linker/MPLIB Object Librarian ................ 142
N
NVM
O
OC/PWM Module Timing Characteristics.......................... 167
Operating Current (I
Operating Frequency vs Voltage
Oscillator
Oscillator Selection ........................................................... 119
Oscillator Start-up Timer
Output Compare Interrupts ................................................. 87
Output Compare Module..................................................... 85
Output Compare Operation During CPU Idle Mode............ 87
Output Compare Sleep Mode Operation ............................ 87
© 2006 Microchip Technology Inc.
Register Map......................................................... 69, 70
Traps........................................................................... 65
Interrupt Stack Frame ................................................. 67
Core Register Map...................................................... 37
Applicability ................................................................. 44
Incrementing Buffer Operation Example..................... 43
Start and End Address................................................ 43
W Address Register Selection .................................... 43
In-Circuit Emulator .................................................... 143
In-Circuit Emulator .................................................... 143
Register Map............................................................... 51
dsPIC30FXXXX-20 (Extended)................................. 145
Configurations........................................................... 122
Operating Modes (Table) .......................................... 120
System Overview ...................................................... 119
Timing Characteristics .............................................. 161
Timing Requirements................................................ 161
Register Map............................................................... 88
Timing Characteristics .............................................. 166
Timing Requirements................................................ 166
Fail-Safe Clock Monitor .................................... 124
Fast RC (FRC) .................................................. 123
Initial Clock Source Selection ........................... 122
Low-Power RC (LPRC)..................................... 123
LP Oscillator Control ......................................... 123
Phase Locked Loop (PLL) ................................ 123
Start-up Timer (OST) ........................................ 122
DD
)..................................................... 147
dsPIC30F2011/2012/3012/3013
P
Packaging Information ...................................................... 183
Peripheral Module Disable (PMD) Registers .................... 131
PICSTART Plus Development Programmer..................... 144
Pinout Descriptions............................................................. 14
PLL Clock Timing Specifications ...................................... 157
POR. See Power-on Reset.
Port Write/Read Example ................................................... 58
PORTB
PORTC
PORTD
PORTF
Power Saving Modes........................................................ 129
Power-Down Current (I
Power-up Timer
Program Address Space..................................................... 27
Program and EEPROM Characteristics............................ 154
Program Counter ................................................................ 18
Programmable .................................................................. 119
Programmer’s Model .......................................................... 18
Programming Operations.................................................... 49
Protection Against Accidental Writes to OSCCON ........... 124
R
Reader Response............................................................. 200
Reset ........................................................................ 119, 125
Marking............................................................. 183, 184
Register Map for dsPIC30F2011/3012 ....................... 59
Register Map for dsPIC30F2012/3013 ....................... 59
Register Map for dsPIC30F2011/2012/3012/3013 ..... 59
Register Map for dsPIC30F2011/3012 ....................... 59
Register Map for dsPIC30F2012/3013 ....................... 60
Register Map for dsPIC30F2012/3013 ....................... 60
Idle............................................................................ 130
Sleep ........................................................................ 129
Sleep and Idle........................................................... 119
Timing Characteristics .............................................. 161
Timing Requirements ............................................... 161
Construction ............................................................... 29
Data Access from Program Memory Using
Data Access From Program Memory Using
Data Access from, Address Generation ..................... 29
Data Space Window into Operation ........................... 32
Data Table Access (LS Word) .................................... 30
Data Table Access (MS Byte) .................................... 31
Memory Map............................................................... 28
Table Instructions
Diagram ...................................................................... 19
Algorithm for Program Flash....................................... 49
Erasing a Row of Program Memory ........................... 49
Initiating the Programming Sequence ........................ 50
Loading Write Latches ................................................ 50
BOR, Programmable ................................................ 127
Brown-out Reset (BOR)............................................ 119
Oscillator Start-up Timer (OST)................................ 119
POR
POR (Power-on Reset)............................................. 125
Program Space Visibility..................................... 31
Table Instructions ............................................... 30
TBLRDH ............................................................. 30
TBLRDL.............................................................. 30
TBLWTH............................................................. 30
TBLWTL ............................................................. 30
Operating without FSCM and PWRT................ 127
With Long Crystal Start-up Time ...................... 127
PD
)................................................ 149
DS70139E-page 195