DSPIC30F2012 Microchip Technology Inc., DSPIC30F2012 Datasheet - Page 108

• Manufacturer Part Number: DSPIC30F2012
• Description: Dspic30f2011/2012/3012/3013 High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F2011/2012/3012/3013
15.9
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a selected capture input (IC1 for UART1 and IC2 for
UART2). To enable this mode, you must program the
input capture module to detect the falling and rising
edges of the Start bit.
15.10 UART Operation During CPU
15.10.1
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is in
progress, then the transmission is aborted. The UxTX
pin is driven to logic ‘1’. Similarly, if entry into Sleep
mode occurs while a reception is in progress, then the
reception is aborted. The UxSTA, UxMODE, transmit
and receive registers and buffers, and the UxBRG
register are not affected by Sleep mode.
If the WAKE bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX pin
will generate a receive interrupt. The Receive Interrupt
Select mode bit (URXISEL) has no effect for this func-
tion. If the receive interrupt is enabled, then this will
wake-up the device from Sleep. The UARTEN bit must
be set in order to generate a wake-up interrupt.
DS70139E-page 106
Auto-Baud Support
Sleep and Idle Modes
UART OPERATION DURING CPU
SLEEP MODE
15.10.2
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
UART OPERATION DURING CPU
IDLE MODE
© 2006 Microchip Technology Inc.