HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet - Page 23

• Manufacturer Part Number: HT46R12A
• Description: Ht46r12a -- A/d Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The PFD (PFD0 or PFD1) output shares pin with PA3,
as determined by options. When the PFD (PFD0 or
PFD1) option is selected, setting PA3 1 ( SET PA.3 )
will enable the PFD output and setting PA3 0 ( CLR
PA.3 ) will disable the PFD output and PA3 output at low
level.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Note:
A/D Converter
The 4 channels and 9-bit resolution A/D (8-bit accuracy)
converter are implemented in this microcontroller. The
reference voltage is VDD. The A/D converter contains
four special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D con-
version is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D con-
version control bit and end of A/D conversion flag. If us-
ers want to start an A/D conversion, define the PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0 1 0). At the end of A/D conversion, the EOCB bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Rev. 1.00
Timer
OFF
OFF
ON
ON
timer/event counter
Preload
X stands for unused
U stands for unknown
M is 256 for PFD
N is preload value for the timer/event counter
f
Timer
Value
T M R
X
X
N
N
is input clock frequency for the
PA3 Data
Register
0
1
0
1
PA3 Pad
State
PFD
U
0
0
f
TMR
Frequency
/[2 (M-N)]
PFD
X
X
X
23
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There s a total of 4
channels to select. The bit5~bit3 of the ADCR are used
to set the PB configurations. PB can be an analog input
or as digital I/O line determined by these 3 bits.
Once a PB line is selected as an analog input, the I/O
functions and pull-high resistor of this I/O line are dis-
abled and the A/D converter circuit is powered on. The
EOCB bit (bit6 of the ADCR) is end of A/D conversion
flag. Check this bit to know when A/D conversion is com-
pleted. The START bit of the ADCR is used to begin the
conversion of the A/D converter. Giving START bit a ris-
ing edge and falling edge means that the A/D conver-
sion has started. In order to ensure that A/D conversion
is completed, the START should remain at 0 until the
EOCB is cleared to 0 (end of A/D conversion).
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to 1
when the START bit is set from 0 to 1 .
Important Note for A/D initialization:
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
PCR2 PCR1 PCR0
0
0
0
0
1
0
0
1
1
x
Port B Configuration
0
1
0
1
x
PB3
PB3
PB3
PB3
AN3
3
PB2
PB2
PB2
AN2
AN2
2
HT46R12A
August 3, 2007
AN1
AN1
AN1
PB1
PB1
1
PB0
AN0
AN0
AN0
AN0
0