HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet
HT46R12A
Related parts for HT46R12A
HT46R12A Summary of contents
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... RAM PFD for audio generation General Description The HT46R12A is an 8-bit, high performance, RISC ar- chitecture microcontroller devices specifically designed for A/D applications that interface directly to analog sig- nals, such as those from sensors. The advantages of low power consumption, I/O flexibil- ...
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... Block Diagram Pin Assignment Rev. 1.00 2 HT46R12A August 3, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 Description +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT46R12A August 3, 2007 ...
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... =0. =0. =0. there may be more STB =5V) if its input voltage is 2.5V HT46R12A Ta=25 C Typ. Max. Unit 5.5 V 5.5 V 0.6 1 0.8 1 0.4V ...
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... Test Conditions Min. V Conditions DD 2 calibraton With 10mV overdrive there may be more STB =5V) if its input voltage is 2.5V HT46R12A Ta=25 C Typ. Max. Unit 4000 kHz 8000 kHz 4000 kHz 8000 kHz 90 180 s 65 130 1024 SYS s s ...
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... Program Counter Program Counter S10~S0: Stack register bits @7~@0: PCL bits 6 HT46R12A * ...
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... It should not be re-en- abled until the TBLH has been backed up. All table re- lated instructions require two cycles to complete the Table Location * Table Location P10~P8: Current program counter bits 7 HT46R12A * August 3, 2007 ...
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... Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through the memory pointer registers, MP0 and MP1. Rev. 1.00 RAM Mapping 8 HT46R12A August 3, 2007 ...
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... Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked, as the EMI bit will be automati- cally cleared. This scheme may prevent any further Function Status (0AH) Register 9 HT46R12A August 3, 2007 ...
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... T1F (bit 5 of the INTC1) and its sub- routine call location is 014H. The related interrupt request flag, T1F, will be reset and the EMI bit cleared to disable further interrupts. Function INTC0 (0BH) Register Function INTC1 (1EH) Register 10 HT46R12A August 3, 2007 ...
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... VDD and process variations. By se- lecting appropriate WDT options, longer time-out peri- ods can be implemented. If the WDT time-out is 16 selected about 4.7s can be achieved. 11 HT46R12A Pin OSC2 can determined by a configuration , then a maximum time-out period of August 3, 2007 ...
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... If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power-down mode. 12 HT46R12A 1 before entering the August 3, 2007 ...
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... Input/Output Ports Input mode Stack Pointer Points to the top of the stack Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise recommended to use the Hi-noise Reset Circuit. Reset Configuration 13 HT46R12A August 3, 2007 ...
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... HT46R12A RES Reset WDT Time-out (HALT) (HALT)* 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu 000H 000H uuuu uuuu ...
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... After this procedure, the timer/event function can be operated normally. Bit0~bit2 of TMR0C can be used to define the pre-scaling stages for the internal clock sources for the timer/event counter. The overflow signal of the timer/event counter are used to generate the PFD signals. 15 HT46R12A August 3, 2007 ...
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... Timer mode (Internal clock) 7 T0M1 11 = Pulse Width measurement mode (External clock Unused Rev. 1.00 Timer/Event Counter 0 Timer/Event Counter 1 PFD Source Option Function =f SYS =f /2 SYS =f /4 SYS =f /8 SYS =f /16 SYS =f /32 SYS =f /64 SYS =f /128 SYS TMR0C (0EH) Register 16 HT46R12A August 3, 2007 ...
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... Event count mode (External clock) 6 T1M0 10= Timer mode (Internal clock) 7 T1M1 11= Pulse Width measurement mode (External clock) 00= Unused Programmable Pulse Generator - PPG This HT46R12A device contains a single 8-bit PPG out- put channel. The PPG has a programmable period of 256 T, where T can be 1/f , 2/f , 4/f SYS SYS 16/f , 32/f ...
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... PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins PC3/C1OUT, PC4/C1VIN+ are all GPIO. PC2 will be automatically set input only, the PC2 output function PC3 will be automatically set input only, the PC3 output function 18 HT46R12A 0) will cause the following ac- August 3, 2007 ...
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... Rev. 1.00 Description Description Prescaler Stage Definition P0f =f S SYS P0f = SYS P0f = SYS P0f = SYS P0f =f /16 S SYS P0f =f /32 S SYS P0f =f /64 S SYS P0f =f /128 S SYS 19 HT46R12A August 3, 2007 ...
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... PPG0 will start counting from the current contents of the preload register. When the PPG0 input is triggered by a C0VO falling edge transition, triggered by a software bit which is cleared to 0 (P0ST or when a PPG0 timer overflow occurs, the PPG0 will stop counting. Rev. 1.00 Description Description ) or not via configuration op- SYS 20 HT46R12A 0) August 3, 2007 ...
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... Input offset voltage cancellation mode and comparator mode selection 5 C1COFM 1: input offset voltage cancellation mode 0: comparator mode 6 C1CMPOP Comparator output; positive logic 7 Unused bit, read as 0 Rev. 1.00 Function CMP0C (1BH) Register Function CMP1C (1CH) Register 21 HT46R12A POR 1000B POR 1000B August 3, 2007 ...
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... PA3 to remain The I/O functions of PA3 are shown below. I/O I/P O/P Mode (Normal) (Normal) Logical Logical PA3 Input Output Note: The PFD frequency is the timer/event counter overflowfrequencydividedby 2. Input/Output Ports 22 HT46R12A I/P O/P (PFD) (PFD) Logical PFD Input (Timer on) August 3, 2007 ...
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... START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selec- tion bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initial- ization is not required. 23 HT46R12A PB3 ...
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... A/D conversion Rev. 1.00 Function ACSR (27H) Register Function ADCR (26H) Register Bit5 Bit4 Bit3 ADRL (24H), ADRH (25H) Register /8 as the A/D clock SYS 24 HT46R12A Bit2 Bit1 Bit0 August 3, 2007 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1. the A/D clock SYS A/D Conversion Timing 25 HT46R12A August 3, 2007 ...
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... Since the low voltage state has to be maintained for over 1ms, after this 1ms delay, the device will enter the reset mode. Rev. 1.00 The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock. Low Voltage Reset 26 HT46R12A and V is shown below. DD LVR August 3, 2007 ...
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... Enable this bit the PPG output will be defined as an active low output PPG0 timer start counting synchronized with clock; P0TSYN. This option is to determine the PPG0 timer start counting is synchronized with input clock or not. Rev. 1.00 Options and HT46R12A August 3, 2007 ...
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... RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.00 28 HT46R12A August 3, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Description 29 HT46R12A Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 30 HT46R12A Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R12A August 3, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.00 PDF PDF PDF addr PDF PDF HT46R12A August 3, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R12A August 3, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.00 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R12A August 3, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.00 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R12A August 3, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.00 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R12A August 3, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.00 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46R12A August 3, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.00 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R12A August 3, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.00 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R12A August 3, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.00 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R12A August 3, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.00 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R12A August 3, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R12A August 3, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.00 PDF PDF PDF HT46R12A August 3, 2007 ...
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... Package Information 24-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 1235 255 125 125 16 50 100 295 345 0 44 HT46R12A Max. 1265 265 135 145 20 70 315 360 15 August 3, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 590 HT46R12A Max. 419 300 20 614 104 August 3, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 46 HT46R12A August 3, 2007 ...
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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 47 HT46R12A August 3, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 48 HT46R12A August 3, 2007 ...