HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet - Page 15

• Manufacturer Part Number: HT46R12A
• Description: Ht46r12a -- A/d Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Timer/Event Counter
Two timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 contains an 8-bit
programmable count-up counter whose clock may be
sourced from an external source or an internal clock
source. The internal clock source comes from f
Timer/Event Counter 1 contains an 8-bit programmable
count-up counter whose clock may come from an exter-
nal source or an internal clock source. The internal clock
source comes from f
lows external events to be counted, time intervals or
pulse widths to be measure.
Using the internal system clock, the timer/event counter
is has only one reference time base. If the timer clock
source is sourced externally then timer intervals can be
measured time intervals or pulse widths measured.
Using the internal clock allows the user to generate an
accurate time base.
There are two registers associated with Timer/Event
Counter 0, TMR0 and TMR0C (0EH) and two registers
for Timer/Event Counter 1, TMR1 and TMR1C. Writing
values into the TMR0 or TMR1 registers places a start
value into the respective Timer/Event Counter 0/1
preload register while reading TMR0 or TMR1 retrieves
the contents of the respective Timer/Event Counter. The
TMR0C and TMR1C registers are the Timer/Event
Counter control registers, which define the operating
mode, the counting enable or disable and define the ac-
tive edge.
The T0M0/T1M0 and T0M1/T1M1 bits in the control reg-
isters define the operation mode. The event count mode
is used to count external events, which means that the
clock source will be sourced from the timer external
pins, TMR0 and TMR1. The timer mode functions as a
normal timer with the clock source coming from the in-
ternally selected clock source. The pulse width mea-
surement mode can be used to measure the duration of
a high or low level signal on either TMR0 or TMR1,
whose time reference is based on the internally selected
clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting from the current contents in the
timer/event counter register and ends at FFH. Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register, and generates an
interrupt request flag, which is the T0F bit in the INTC0
register or the T1F bit in the INTC1 register.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to 1 , after the
respective Timer/Event counter has received a transient
from low to high, or high to low dependent upon the
value of the T0E/T1E bit, it will start counting until the re-
spective logic level on the TMR0 or TMR1 pin returns to
its original level and resets the T0ON/T1ON bit. The
Rev. 1.00
SYS
/4. The external clock input al-
SYS
.
15
measured result remains in the timer/event counter
even if the activated transient occurs again, as only a
single 1-cycle measurement is made. Not until the
T0ON/T1ON bit is once again set can further measure-
ments be made. In this operational mode, the
timer/event counter begins counting not according to
the logic level but according to the transient edges. In
the case of a counter overflow, the counter is reloaded
from the timer/event counter register and issues an in-
terrupt request, as in the other two modes, i.e.the event
and timer modes.
To enable the counting operation, the Timer ON bit,
namely the T0ON bit of TMR0C or the T1ON of TMR1C,
should be set to 1. In the pulse width measurement
mode, the T0ON/T1ON is automatically cleared after
the measurement cycle is completed. But in the other
two modes, the T0ON/T1ON can only be reset by in-
structions. The overflow of the Timer/Event Counters is
one of the wake-up sources. The Timer/Event Counters
can also be use to drive a PFD (Programmable Fre-
quency Divider) output on pin PA3, selected via configu-
ration options. Only one PFD, (PFD0 or PFD1) can be
used with PA3 selected via configuration options. No
matter what the operation mode is, writing a 0 to ET0I or
ET1I disables the related interrupt service. When the
PFD function is selected, executing a SET [PA].3 in-
struction will enable the PFD output while executing a
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. However if
the timer/event counter is already on, any data written to
the timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter will
continue normal operation until an overflow occurs.
When the timer/event counter is read, the clock is
blocked to avoid errors, and as this may results in a
counting error, his should be taken into account by the
programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1 registers first, before turning on the re-
lated timer/event counter, as the initial power on value of
the TMR0/TMR1 registers are unknown. Due to the
timer/event structure, the programmer should pay spe-
cial attention when using instructions to enable then dis-
able the timer for the first time, whenever there is a need
to use the timer/event function, to avoid unpredictable
results. After this procedure, the timer/event function
can be operated normally.
Bit0~bit2 of TMR0C can be used to define the pre-scaling
stages for the internal clock sources for the timer/event
counter. The overflow signal of the timer/event counter
are used to generate the PFD signals.
CLR [PA].3 instruction will disable the PFD output.
HT46R12A
August 3, 2007