HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet - Page 17

• Manufacturer Part Number: HT46R12A
• Description: Ht46r12a -- A/d Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Programmable Pulse Generator - PPG
This HT46R12A device contains a single 8-bit PPG out-
put channel. The PPG has a programmable period of
256 T, where T can be 1/f
16/f
width.
The PPG detects the falling edge of a trigger input, and
then outputs a single pulse. The falling edge trigger may
be sourced from either comparators or from a software
trigger bit, which can be selected by software. The PPG
is capable of generating pulse widths ranging from
0.25 s to 8.192ms for a system frequency of 4MHz. An
active low or active high output can be selected for the
PPG via a configuration option. Writing
PPGT0 register yields a pulse width of 256 T output.
Rev. 1.00
PPG0 functional description
The PPG0 module consists of PPG0 timers, a PPG
Mode Control, and two comparators. The PPG0 timer
consists of a prescaler, one 8-bit up-counter timer,
PPG0C control register
CMP0EN: Enables or disables Comparator 0 (0: disable, 1: enable)
CMP1EN: Enables or disables Comparator 1 (0: disable, 1: enable)
P0PSC2, P0PSC1, P0PSC0: These three bits select the PPG0 timer prescaler rate.
P0SPEN: Enables or disables the stopping of the PPG0 timer using the C0VO trigger input (0: disable, 1: enable)
P0RSEN: Enables or disables the restarting of the PPG0 timer using the C1VO trigger input. (0: disable, 1: enable)
P0ST: PPG0 software trigger bit. (0: Stop PPG0, 1: Restart PPG0)
PPG0C (20H)
POR value
SYS
Bit No.
0~2
, 32/f
3
4
5
6
7
Bit No.
SYS
, 64/f
SYS
T1ON
Label
T1M0
T1M1
T1E
, 128/f
P0ST
7
0
SYS
SYS
, 2/f
Unused bit, read as 0
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting (0= disable; 1= enable)
Unused bit, read as 0
Define the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
P0RSEN
for an output pulse
SYS
6
0
, 4/f
00H to the
SYS
TMR1C (11H) Register
P0SPEN
, 8/f
5
0
SYS
,
17
P0PSC2
4
0
and an 8-bit preload data register. The programmable
pulse generator starts counting from the current con-
tents in the preload register and ends at FFH
00H . Once an overflow occurs, the counter is re-
loaded from the PPG0 timer counter preload register,
and generates a signal to stop the PPG timer. The
software trigger bit, P0ST, will be cleared when a PPG
timer overflow occurs.
There are two registers related to the PPG0 output
function, a control register, PPG0C, and a timer
preload register, PPGT0. The control register,
PPG0C, defines the PPG0 input control mode trigger
source, the enable or disable of the comparators, de-
fines the PPG0 timer prescaler rate which have value
of f
f
using the C0VO triggered input, enable or disable the
restarting of the PPG0 timer using the C1VO triggered
input, and control the PPG0 software trigger bit to trig-
ger the PPG0 timer On or Off. The PPGT0 register is
the PPG0 preload register, whose contents determine
the output pulse width.
SYS
SYS
/128, enable or disable stopping the PPG0 timer
Function
/1, f
P0PSC1
SYS
3
0
/2, f
SYS
P0PSC0
/4, f
2
0
SYS
/8, f
SYS
CMP1EN CMP0EN
/16, f
1
0
HT46R12A
August 3, 2007
SYS
/32, f
0
0
SYS
/64,