RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet - Page 18
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RS5C313
Manufacturer Part Number
RS5C313
Description
Ultra-compact Real-time Clock Ic
Manufacturer
RICOH Co.,Ltd.
Datasheet
1.RS5C313.pdf
(27 pages)
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18
RS5C313
5. Oscillator Halt Sensing
Oscillation Halt can be sensed by setting the XSTP (oscillator halt sensing) bit to 0 (after writing data to the control
register) and then monitoring the XSTP bit. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This
function can be applied to judge clock data validity.
6. Typical Power Supply Circuit
*
*
XSTP
OSCOUT
R S 5 C 3 1 3
1)
2)
Ensure error-free oscillation halt sensing by preventing the following:
1) Instantaneous disconnection of V
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the indi-
OSCIN
INTR
VDD
While the CE pin is held at the low level the XSTP bit is set to 1 upon power-on from 0 V. Note that any instantaneous power disconnection may
Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
VSS
cause operational failure. When the CE pin is held at the high level oscillation halt is not sensed and the value of the XSTP bit when the CE pin is
held at the low level is retained.
vidual pins of the IC
Power-on
from 0V
*
1
Considerations in Use of XSTP Bit
Writing of data to
control register
(in the presence of oscillation)
A
B
System supply voltage
DD
Oscillation halt
1) Connect the capacitance of the oscillation circuit to the VSS pin.
2) Mount the high- and low-frequency by-pass capacitors in parallel
3) Connect the pull-up resistor of the INTR pin to two different posi-
4) Timing of power supply on / off and CE terminal refer to lower part
V
CE
DD
and very close to the RS5C313.
tions depending on whether the resistor is in use during battery
back-up.
plan.
0V
Oscillation restart
C,D,E : The lower limit voltage for CPU operation
• When not in use during battery back-up
• When in use during battery back-up
MIN. 0µs
C
0.2V
System supply
*
2
DD
voltage
- - - - - Position A in the left figure
- - - - - Position B in the left figure
0.2V
DD
MIN. 0µs
D
Battery voltage
MIN. 0µs
E
0.2V
DD