RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet
RS5C313
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RS5C313 Summary of contents
Page 1
... RS5C313 OUTLINE The RS5C313 is a CMOS type real-time clock which is connected to the CPU via three signal lines and capable of serial transmission of clock and calendar data to the CPU. The RS5C313 can generate various interrupt clock pulses lasting for long periods (one month). Driving an oscillation circuit at constant voltage, the circuit undergoes few voltage fluctuations and consequently realizes low current consumption (TYP. 0.7 µ ...
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... RS5C313 BLOCK DIAGRAM OSCIN OSC OSCOUT OSC DETECT VDD VOLTAGE REGULATOR VSS INTR APPLICATIONS • Communication equipment (Multi-function telephone, portable telephone, PHS, Pager) • Office automation (Facsimile, portable facsimile) • Personal computer (Desk top type, notebook type, word proccesor, PDA, electronic notebook, TV games) • ...
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... These pins configure an oscillation circuit by connecting a 32.768 kHz crystal oscillator between the OSCIN and OSCOUT pins and by connecting a capacitor between the OSCIN and V pins. SS (Any other oscillation circuit components are built into the RS5C313.) The VDD pin is connected to a power supply and the V ground. RS5C313 pin is connected to the ...
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... RS5C313 ABSOLUTE MAXIMUM RATINGS Symbol Item V Supply voltage DD V Input voltage I V Output voltage1 O1 V Output voltage2 O2 P Maximum power consumption D Topt Ambient operating temperature Tstg Storage temperature Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions ...
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... SCLK SIO INTR V =10V I/O=OPEN V =5. I/O=OPEN OSCOUT RS5C313 (V =0V, Topt=–30 to +80˚C) SS MIN. TYP. MAX. Unit 2.7 5.0 6.0 V 1.6 6.0 V 32.768 kHz =6pF, R =30kΩ), C =10pF MIN. TYP. ...
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... RS5C313 AC CHARACTERISTICS Symbol Item t CE set-up time CES t CE hold time CEH t CE recovery time CR t SCLK clock cycle SCK t SCLK “H” clock time CKH t SCLK “L” clock time CKL t SCLK clock set-up time CKS t Data output start time (from ...
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... Interrupt cycle register CT 3 1-day counter D 8 10-day counter — 1-month counter MO 8 10-month counter — 1-year counter Y 8 10-year counter Y 80 Control register CTFG Test register — RS5C313 1 Data ...
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... RS5C313 2. Register 2.1 Control Register (at Eh CTFG 12/24 WTEN CTFG 12/24 XSTP 2.1-1 (ADJ) When the ADJ bit is set to 1: (If the WTEN bit is 0, adjustment of second digits is started after the WTEN bit is set to 1.) 1) For second digits ranging from seconds: 2) For second digits ranging from seconds: ...
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... MAX. 122.1µs Completion of second digit adjustment MAX.91.6µs End of second digit increment by 1 91.6µs End of second digit carry pulse Note 12(AM12) 12 01( 02( 03( 04( 05( 06( 07( 08( 09( 10(AM10) 22 11(AM11) 23 RS5C313 32(PM12) 21(PM 1) 22(PM 2) 23(PM 3) 24(PM 4) 25(PM 5) 26(PM 6) 27(PM 7) 28(PM 8) 29(PM 9) 30(PM10) 31(PM11) 9 ...
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... RS5C313 2.1-6 (CTFG) The CTFG bit is set to 1 when interrupt pulses are output from the INTR pin held at the low level. There are two interrupt modes selectable: the pulse mode (when the CT the CT bit is set to 1). 3 The CTFG bit can be set only when the CT level while setting the CTFG bit to 0 turns off the INTR pin ...
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... The TEST bit should be fixed at 1 for ordinary operation and will automatically be set to 1 when the CE pin is at the low level. * (For write operation) 0 (For read operation) 0 Bits for selecting the interrupt cycle and output mode at the INTR pin * bit is set to 1). 3 (For write operation) (For read operation Bit For Testing 2 * TEST 0 Testing mode 1 Ordinary operating mode RS5C313 1 Description 11 ...
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... RS5C313 3. Counters 3.1 Clock Counter ( 5h P The “ ” mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle. ...
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... Ah) 1 (read and write cycle) 10-month calendar digit (at Bh) (read and write cycle) 1-year calendar digit (read and write cycle) 10-year calendar digit RS5C313 (at 8h) (at 9h) (at Ch) (at Dh) 13 ...
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... RS5C313 USAGES 1. Read Data The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable interfac- ing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization with shift clock pulses from the SCLK pin. ...
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... R Address bits Control bits Data bits Writing to Setting of address register control bits RS5C313 R (Hi-z) End of write operation 15 ...
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... Switching the CE pin to the low level or opening it disables both the SCLK and SIO pins, causing high impedance and resetting the internal interfacing circuits such as the shift register. 3) The CE pin should be held at the low level or open state when no access is made to the RS5C313. The CE pin incorpo- rates a pull-down resistor. ...
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... AC coupling - - - - - Permissible except that unpredictable results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) Avoid using the oscillator output of the RS5C313 (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation. Typical external device: ...
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... Connect the capacitance of the oscillation circuit to the VSS pin. System supply voltage 2) Mount the high- and low-frequency by-pass capacitors in parallel and very close to the RS5C313. 3) Connect the pull-up resistor of the INTR pin to two different posi- tions depending on whether the resistor is in use during battery back-up. • ...
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... R1 value of 30k ohms. L range from 5 to 24pF and 8 to 20pF, respectively. When you need to change the frequency to get higher with its oscillation frequency by adjusting the angle of rotation of the variable capacitance of G RS5C313 level and ...
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... RS5C313 After adjustment, oscillation frequency is subject to fluctuations of an ambient temperature and supply voltage. See “10. Typical Characteristic Measurements”. Any rise or fall in ambient temperature from its reference value ranging from degrees Celsius causes a time delay for a 32kHz crystal oscillator recommendable, therefore, to set slightly high oscillation frequency at room temperature ...
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... Connect the capacitance of the oscillation circuit to the VSS pin. 2) Mount the high- and low-frequency by-pass capacitors in parallel and very close to the RS5C313. 3) Connect the pull-up resistor of the INTR pin to two different positions depending on whether the resistor is in use during bat- tery back-up. ...
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... RS5C313 10. Typical Characteristic Measurements VDD OSCIN A OSCOUT VSS INTR 10.1 Standby Current vs. C 2.0 1 10.3 Operational Current vs. SCLK Frequency 1 0.1 V =5V DD 0.01 0.001 0.01 0.1 SCLK Frequency (MHz) 22 VDD =10pF G X'tal : R T =25˚C opt Input pin : Output pin : Open Frequency counter (V =3V) 10 ...
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... V (V) DS 10.6 Oscillation Frequency Deviation vs (f0 –1 –2 –3 – 10.8 Oscillation Start Time vs. V =10pF G 1.0 0.5 0.0 80 100 0 Topt=25˚C 1.5 2.0 RS5C313 DD =4V reference) C =10pF, Topt=25˚ ( Topt=25˚C C =20pF G C =10pF ...
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... RS5C313 11. Typical Software-based Operations 11.1 Initialization upon Power-on Start Power-on YES XSTP=0? No Interrupt cycle register←0h Control register←3h, 7h BSY=0? YES * Control register←0h, 4h Set clock and calendar counters and interrupt cycles. 11.2 Write Operation to Clock and Calendar Counters CE=H Control register←0h, 4h BSY=0? ...
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... Select the level mode as an interrupt mode by setting the CT3 bit Write 2h for the 12-hour format or 6h for the 24-hour format Complete read operation within an interrupt cycle after interrupt generation * (e.g. within 1 second). RS5C313 Read 1-second digit clock counter. Read from clock and calendar counters. Again read 1-second digit ...
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... RS5C313 11.4 Second-digit Adjustment by ±30 seconds Control register ←3h 11.5 Oscillation Start Judgment Power-on YES XSTP=0? NO Control register ←2h, 6h Oscillation start 11.6 Interrupt Operation (a) Cyclic Interrupt Operation (Every 1 Second to 1 Month) Set interrupt cycle register Interrupt to CPU CTFG=1? YES * Control register ←2h, 6h Cyclic interrupt operation ...
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... RS5C313 is set to 3V, a total current consumption can be calculated at about 1.1µ this typical operation, alarm time is stored in the CPU and collated with * clock time through interrupt operation ...