RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet - Page 14

• Manufacturer Part Number: RS5C313
• Description: Ultra-compact Real-time Clock Ic
• Manufacturer: RICOH Co.,Ltd.

14
RS5C313
USAGES
1. Read Data
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable interfac-
ing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin.
The input data are registered in synchronization with the falling edge of the SCLK. When the data is read, the read
cycle shall be set by control bits.
• Control bits
• Address bits
1.1 Read Cycle Flow
1. The CE pin is switched from the low level to the high level.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
3. The SIO pin enters the output mode at the rising edge of the shift clock pulse 2B from the SCLK pin while the
4. Then, the SIO pin returns to the input mode at the rising edge of the shift clock pulse 1C. Afterwards control bits and
5. At the end of read cycle, the CE pin is switched from the high level to the low level (after
*
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0.
four read bits (MSB→LSB) at designated addresses are output at the rising edge of the shift clock pulse 5B (see
the figure below).
address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
the eighth shift clock pulse from the SCLK pin). (Following on read cycle, write operation can be performed by setting
control bits in the write mode at the shift clock pulse 1C and later with the CE pin held at the high level.)
) In the above figure, the “
Output from
SIO pin
(Internal processing)
Input to
SIO pin
SCLK
CE
the
and the diagonaliy shaded area indicates high or low.
“ ”
mark indicates data which are available when the SIO pin is held at the high, low, or Hiz level ;
Reading to shift register
*
1A
(Hi-z)
*
A3 to A0: Inputs the bits MSB to LSB in the address table describing the functions.
2A
R/W AD
Control bits
*
R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
”mark indicates arbitrary data; the “—” mark indicates unknown data;
AD: Writes succeeding address bits (A3 to A0) to the address register when set to 1 with the
DT: Writes data bits (D3 to D0) to the counter or register specified by the address register
3A
4A
DT bit set to 0 and performs no such write operation in any other case.
which has written just before when set to 1 with the R/W and AD bits set equally to 0 and
performs no such write operation in any other case.
DT
Setting of
control bits
5A
A3
Address bits
6A
A2
7A
A1
8A
Writing to
address register
A0
1B
Setting of
SIO pin in
output mode
2B
—
3B
—
4B
Shifting data
—
5B
D3
(Hi-z)
6B
Read data
D2
7B
D1
Setting of SIO pin in
input mode
8B
D0
1C
t
CEH
(Hi-z)
2C
R/W AD
from the falling edge of
3C