BGB101 NXP Semiconductors, BGB101 Datasheet - Page 13

• Manufacturer Part Number: BGB101
• Description: 0 Dbm Bluetooth Radio Module
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Timing Parameters
Notes
1. The S_EN signal going high switches the synthesiser on if preceded by S_DATA / S_CLK activity; the S_EN signal
2. The DCXCTR signal in TX mode serves to switch on the TX output inside the module (see also table 6). It should go
3. A single short S_EN pulse (without preceding S_DATA / S_CLK activity) serves to power-down the IC. It may be
4. Because the VCO is directly modulated by the T_GFSK signal, the DC level on this pin should be present early on
5. The DCXCTR signal (in RX mode) should go low at the actual end of the trailer sequence. The timing for this
REFERENCES
[1] Bluetooth test specification - RF, 20001-07-02, rev. 0.91, 20.B.353/0.91
2003 Aug 05
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
PARAMETER
0 dBm Bluetooth radio module
going low disables the synthesizer in order to perform open-loop modulation or demodulation. Simultaneously, it
enables the receiver chain in RX mode. The length of the S_EN signal should be long enough for the synthesizer
loop to settle.
high a sufficiently long time before the synthesizer loop is disabled ( by bringing the S_EN signal low) in order to allow
the synthesizer loop to resettle. Doing this brings about a considerable reduction in Initial Carrier Frequency
Tolerance and can give a clear improvement in link set-up time.
omitted at the cost of increased power consumption. Any subsequent S_EN pulse without preceding
S_DATA / S_CLK activity toggles between power-up and power-down states, but brings the module into an
undefined power-up state. This mode should be avoided.
during the synthesizer settling phase. Also in RX mode, there should be a well-defined and stable DC voltage on this
pin.
transition should be directly derived from the Access Code detection algorithm inside the baseband processor.
S_DATA last bit to REFCLK enable
S_EN falling edge to REFCLK disable
S_DATA last bit to S_EN rising edge
S_EN width
DCXCTR rising edge before S_EN falling edge
DCXCTR falling edge before S_EN falling edge
T_GFSK last bit to S_EN pulse start
R_DATA last bit to S_EN pulse start
S_EN pulse width
S_DATA last bit to T_GFSK DC bias
S_EN falling edge to T_GFSK first data bit
S_EN falling edge to R_DATA earliest data bit
S_EN falling edge to DCXCTR high
DCXCTR width (in RX mode)
DESCRIPTION
13
note 1
note 2
note 2
note 3
note 4
note 5
CONDITIONS
0.1
0.1
180
0.1
15
MIN.
Preliminary specification
2
185
60
55
2
2
2
2
20
tbd
tbd
TYP.
BGB101
UNIT
s
s
s
s
s
s
s
s
s
s
s
s
s
s