KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 6

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

MIB (Management Information Base) Counters.............................................................................................78
Absolute Maximum Ratings
Operating Ratings
Electrical Characteristics
Timing Specifications.......................................................................................................................................82
November 2005
Micrel Confidential
Bank 16 Transmit Control Register (0x00): TXCR .......................................................................................................................... 57
Bank 16 Transmit Status Register (0x02): TXSR............................................................................................................................ 58
Bank 16 Receive Control Register (0x04): RXCR........................................................................................................................... 58
Bank 16 TXQ Memory Information Register (0x08): TXMIR ........................................................................................................... 59
Bank 16 RXQ Memory Information Register (0x0A): RXMIR .......................................................................................................... 59
Bank 17 TXQ Command Register (0x00): TXQCR ......................................................................................................................... 60
Bank 17 RXQ Command Register (0x02): RXQCR ........................................................................................................................ 60
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ........................................................................................................... 60
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR........................................................................................................... 61
Bank 17 QMU Data Register Low (0x08): QDRL ............................................................................................................................ 61
Bank 17 QMU Data Register High (0x0A): QDRH .......................................................................................................................... 61
Bank 18 Interrupt Enable Register (0x00): IER ............................................................................................................................... 62
Bank 18 Interrupt Status Register (0x02): ISR ................................................................................................................................ 62
Bank 18 Receive Status Register (0x04): RXSR ............................................................................................................................ 63
Bank 18 Receive Byte Count Register (0x06): RXBC..................................................................................................................... 64
Bank 18 Early Transmit Register (0x08): ETXR.............................................................................................................................. 64
Bank 18 Early Receive Register (0x0A): ERXR .............................................................................................................................. 65
Bank 19 Multicast Table Register 0 (0x00): MTR0.......................................................................................................................... 65
Bank 19 Multicast Table Register 1 (0x02): MTR1.......................................................................................................................... 65
Bank 19 Multicast Table Register 2 (0x04): MTR2.......................................................................................................................... 65
Bank 19 Multicast Table Register 3 (0x06): MTR3.......................................................................................................................... 66
Bank 19 Power Management Control and Status Register (0x08): PMCS ..................................................................................... 66
Banks 20 – 31: Reserved................................................................................................................................................................ 67
Bank 32 Chip ID and Enable Register (0x00): CIDER .................................................................................................................... 67
Bank 32 Chip Global Control Register (0x0A): CGCR .................................................................................................................... 67
Banks 33 – 41: Reserved................................................................................................................................................................ 67
Bank 42 Indirect Access Control Register (0x00): IACR ................................................................................................................. 68
Bank 42 Indirect Access Data Register 1 (0x02): IADR1 ................................................................................................................ 68
Bank 42 Indirect Access Data Register 2 (0x04): IADR2 ................................................................................................................ 68
Bank 42 Indirect Access Data Register 3 (0x06): IADR3 ................................................................................................................ 68
Bank 42 Indirect Access Data Register 4 (0x08): IADR4 ................................................................................................................ 68
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5................................................................................................................ 68
Bank 43 – 44: Reserved ................................................................................................................................................................. 69
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR .......................................................................................... 69
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR ............................................................................................ 70
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR.................................................................................................................. 71
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR ................................................................................................................ 71
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR .................................................................................. 71
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR ......................................................................... 72
Bank 46: Reserved ......................................................................................................................................................................... 72
Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT ................................................................................................................... 72
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL............................................................................................ 73
Bank 48: Reserved ......................................................................................................................................................................... 73
Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD ..................................................................................... 74
Bank 49 Port 1 Control Register 4 (0x02): P1CR4.......................................................................................................................... 75
Bank 49 Port 1 Status Register (0x04): P1SR ................................................................................................................................ 76
Banks 50 – 63: Reserved................................................................................................................................................................ 77
Additional MIB Information .............................................................................................................................................................. 79
Asynchronous Timing without using Address Strobe (ADSN = 0)................................................................................................... 82
(1)
..........................................................................................................................................80
(1)
..............................................................................................................................81
(1)
..........................................................................................................................80
6
KSZ8841-16/32 MQL/MVL
Rev 1.3