KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 17

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

November 2005
Micrel Confidential
Pin
Number
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
PMEN
SRDYN
INTRN
LDEVN
RDN
EECS
ARDY
CYCLEN
NC
DGN
VDD
VLBUSN
EEEN
P1LED3
EEDO
CO
D
Opd
Gnd
Ipd
Ipd
Type
Opu
O
Opd
Opd
Ipd
Opu
Ipd
Opd
P
Opd
Opd
pu
AEN, A15-A1, and the content of the BANK select register.
Power Management Event Not
When asserte
occurred in the system when a wake-up signal is de
Synchronous Ready Not
Ready signal to interface with synchronous bus for b
extend accesses.
F
sy
F r burst mode (32-bit interfa
w it states.
Interrupt
Active Low ignal to host CPU
a
Local Device Not
A
K
L
Read Strobe Not
Asynchronous read strobe, active Low.
EEPROM Chip Select
T
A
ARDY may be used when interfacing asy
c
Cycle N
For VLBus-like mode cycle signal; this pin follows the addressing cycle to si
command cycle.
For burst mode (32-bit interface only), this pin
write cycles.
No Connect
Digital IO grou
1.2V digital co
output pin pro
Note: Internally
to this pin. Thi
capacitors).
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like b
mode.
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
Port 1 LED indicator
See the description in pins 3, 4, and 5.
Pin Function
EEPROM Data Out
ycles. It is
n external
DEVN is a combinational decode of the Address and AEN signal.
or VLBus-like mode, the falling edge of this signal indicates ready. This signal is
o
his signal
a
ctive Low
SZ8841M address programmed into the high byte of the base address register.
synchrono
nchronous to the bus clock signal BCLK.
ot
s
output signal, ass
is used to select a
asynchronous to the host CPU or bus clock.
4.7K pull-up resis
us Ready
17
vides power to VDDC, VDDA and VDDAP pins.
d (Low), this signal indicates that a power management event has
s
re voltage output (internal 1.2V LDO power supply output), this 1.2V
nd
generated power voltage. Do not connect an external power supply
p
in is used for connecting external filter (Ferrite bead and
erted wh
ce only), the KSZ8841M drives this pin low
tor
n exte
to indica
rnal EEPROM
en AEN is L
te an interrupt status bit is set, this pin need
nchronous buses to extend bus access
stays High for read cycles and Low for
ow and A15-
dev
tected by KSZ8841M.
oth EISA-like and VLBus-like
ice.
KSZ8841-16/32 MQL/MVL
A4 decode to the
to signal
gnal the
Rev 1.3
urst