KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 5

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

CPU Interface I/O Registers .............................................................................................................................37
Register Map: MAC and PHY ...........................................................................................................................46
November 2005
Micrel Confidential
Asynchronous Interface .................................................................................................................................................................. 29
Synchronous Interface .................................................................................................................................................................... 30
BIU Summation............................................................................................................................................................................... 30
BIU Implementation Principles ........................................................................................................................................................ 31
Queue Management Unit (QMU)................................................................................................................................ 32
Transmit Queue (TXQ) Frame Format ............................................................................................................................................ 32
Receive Queue (RXQ) Frame Format ............................................................................................................................................ 33
EEPROM Interface ...................................................................................................................................................... 34
Loopback Support...................................................................................................................................................... 36
Near-end (Remote) Loopback......................................................................................................................................................... 36
I/O Registers ................................................................................................................................................................................... 37
Internal I/O Space Mapping ............................................................................................................................................................ 38
Bit Type Definition........................................................................................................................................................................... 46
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks).................................................................................... 46
Bank 0 Base Address Register (0x00): BAR................................................................................................................................... 46
Bank 0 Bus Error Status Register (0x06): BESR ............................................................................................................................ 47
Bank 0 Bus Burst Length Register (0x08): BBLR............................................................................................................................ 47
Bank 1: Reserved ........................................................................................................................................................................... 47
Bank 2 Host MAC Address Register Low (0x00): MARL ................................................................................................................ 48
Bank 2 Host MAC Address Register Middle (0x02): MARM............................................................................................................ 48
Bank 2 Host MAC Address Register High (0x04): MARH ............................................................................................................... 48
Bank 3 On-Chip Bus Control Register (0x00): OBCR ..................................................................................................................... 49
Bank 3 EEPROM Control Register (0x02): EEPCR ........................................................................................................................ 49
Bank 3 Memory BIST Info Register (0x04): MBIR........................................................................................................................... 50
Bank 3 Global Reset Register (0x06): GRR.................................................................................................................................... 50
Bank 3 Power Management Capabilities Register (0x08): PMCR .................................................................................................. 50
Bank 3 Wakeup Frame Control Register (0x0A): WFCR ................................................................................................................ 52
Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0 ......................................................................................................... 52
Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1 ......................................................................................................... 53
Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0 ................................................................................................. 53
Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1 ................................................................................................. 53
Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2 ................................................................................................. 53
Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3 ................................................................................................. 53
Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0 ......................................................................................................... 54
Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1 ......................................................................................................... 54
Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0 ................................................................................................. 54
Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1 ................................................................................................. 54
Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2 ................................................................................................. 54
Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3 ................................................................................................. 55
Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0 ......................................................................................................... 55
Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1 ......................................................................................................... 55
Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0 ................................................................................................. 55
Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1 ................................................................................................. 55
Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2 ................................................................................................. 56
Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3 ................................................................................................. 56
Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0 ......................................................................................................... 56
Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1 ......................................................................................................... 56
Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0 ................................................................................................. 56
Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1 ................................................................................................. 57
Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2 ................................................................................................. 57
Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3 ................................................................................................. 57
Bank 8 – 15: Reserved ................................................................................................................................................................... 57
5
KSZ8841-16/32 MQL/MVL
Rev 1.3