KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 21

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Func
The KSZ8841M is a single-chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver (PHY), a
MAC, and a Bus Interface Unit (BIU) that controls the KSZ8841M via an 8-bit, 16-bit, or 32-bit host bus interface.
The KSZ8841M is fully compliant to IEEE802.3u standards.
Functional Overview
Powe
Powe
The KSZ8841M features a port power-down mode. To save power, the user can power-down the port that is not in use by
setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these registers.
In addition, there is a full chip power-down mode PWRDN (pin 36). When this pin is pulled-down, the entire chip powers
down.
Wake-on-LAN
Wake-up frame events are used to wake
network. Examples of meaningful data inc
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is
pre-programmed by the policy owner or oth
traffic.
A wak
powered state (working).
A wake-up signal is caused by:
1. Det
2. Receipt of a network wake-up frame
3. Receipt of a Magic Packet
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in
their own way.
Link Change
Link status wake events are useful to indicate a change in the network’s availability, especially when this change may
impact the level at which the system should re-enter the sleeping state. For example, a change from link off to link on may
trigger
transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2) since the
network is not currently available.
Wake
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.
The KSZ8841M supports up to four users defined wake-up frames as below:
1. Wake-up frame 0 is defined in registers 0x00-0x0A of Bank 4 and is enabled by bit 0 in wakeup frame control register.
2
3. Wake-up frame 2 is defined in regist
4. Wake-up frame 4 is defined in registers 0x00-0x0A of Bank 7 and is enabled by bit 3 in wakeup frame control register.
1
more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.
November 2005
Micrel Confidential
. Wake-up frame 1 is defined in registers 0x00-0x0A of Bank 5 and is enabled by bit 1 in wakeup frame control register.
References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI. For
r dow
-up Packet
ection
Tran
e-up
r M
the
tio
system to re-enter sleep at a higher level (D2 versus D3
anage
sitioning
nal D
n
event
of a ch
is a r
men
escripti n
ang
this pin
e in the n
t
equest
from
o
for h
etwo
pull-
ardwa
rk link
down
ers 0x00-0x0A of Bank 6 and is enabled by bit 2 in wakeup frame control register.
lude the
er softwa
to pull-up results in a power up and chip reset.
re and/o
the syst
state
em whenever meaningful data is presented to the system over the
reception of a Magic Packet, a management request from a remote
r software external to the network device to put the system into a
re with information on how to identify wake frames from other network
21
1
) so that wake frames can be detected. Conversely, a
KSZ8841-16/32 MQL/MVL
Rev 1.3