PIC16C774 Microchip Technology Inc., PIC16C774 Datasheet - Page 20

• Manufacturer Part Number: PIC16C774
• Description: 28/40-pin, 8-bit Cmos Microcontrollers W/ 12-bit A/d
• Manufacturer: Microchip Technology Inc.

PIC16C77X
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-7:
DS30275A-page 20
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: PSPIF is reserved on the 28-pin devices, always maintain this bit clear.
PSPIF
R/W-0
(1)
PIR1 REGISTER
PSPIF
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1 REGISTER (ADDRESS 0Ch)
(1)
: Parallel Slave Port Read/Write Interrupt Flag bit
RCIF
R-0
TXIF
R-0
SSPIF
R/W-0
Advance Information
CCP1IF
R/W-0
TMR2IF
R/W-0
Note:
TMR1IF
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1999 Microchip Technology Inc.
read as ‘0’