PIC16C774 Microchip Technology Inc., PIC16C774 Datasheet - Page 126

• Manufacturer Part Number: PIC16C774
• Description: 28/40-pin, 8-bit Cmos Microcontrollers W/ 12-bit A/d
• Manufacturer: Microchip Technology Inc.

PIC16C77X
11.10
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be configured for RC
(ADCS1:ADCS0 = 11b). With the RC clock source
selected, when the GO/DONE bit is set the A/D module
waits one instruction cycle before starting the conver-
sion cycle. This allows the SLEEP instruction to be exe-
cuted, which eliminates all digital switching noise
during the sample and conversion. When the conver-
sion cycle is completed the GO/DONE bit is cleared,
and the result loaded into the ADRESH and ADRESL
registers. If the A/D interrupt is enabled, the device will
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction causes the present conver-
sion to be aborted and the A/D module is turned off,
though the ADON bit will remain set.
TABLE 11-3
DS30275A-page 126
Address
0Bh,8Bh,
10Bh,18Bh
0Ch
8Ch
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
1Eh
9Eh
9Bh
1Fh
9Fh
05h
06h
09h
85h
86h
89h
(2)
(2)
2: These bits/registers are not implemented on the 28-pin devices, read as ’0’.
A/D Operation During Sleep
Name
INTCON
PIR1
PIE1
ADRESH A/D High Byte Result Register
ADRESL
REFCON
ADCON0
ADCON1
PORTA
PORTB
PORTE
TRISA
TRISB
TRISE
SUMMARY OF A/D REGISTERS
A/D Low Byte Result Register
PORTB Data Latch when written: PORTB pins when read
PORTB Data Direction Register
PSPIF
PSPIE
VRHEN
ADCS1
ADFM
Bit 7
GIE
IBF
—
—
—
(1)
(1)
VRLEN
ADCS0
VCFG2
PEIE
ADIF
ADIE
Bit 6
OBF
—
—
—
PORTA5
bit5
VRHOEN
VCFG1
RCIF
RCIE
CHS2
Bit 5
T0IE
IBOV
(2)
—
Advance Information
(2)
PORTA Data Latch when written: PORTA<4:0> pins when read
PORTA Data Direction Register
PSPMODE
VRLOEN
VCFG0
CHS1
INTE
TXIF
TXIE
Bit 4
—
SSPIF
SSPIE
PCFG3
RBIE
CHS0
Bit 3
—
—
—
Turning off the A/D places the A/D module in its lowest
current consumption state.
11.11
Since the analog inputs employ ESD protection, they
have diodes to V
analog input must be between V
voltage exceeds this range by greater than 0.3V (either
direction), one of the diodes becomes forward biased
and it may damage the device if the input current spec-
ification is exceeded.
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 2.5 k recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
Note:
PORTE Data Direction Bits
GO/DONE
CCP1IE
CCP1IF
PCFG2
Bit 2
T0IF
RE2
Connection Considerations
—
For the A/D module to operate in SLEEP,
the A/D clock source must be configured to
RC (ADCS1:ADCS0 = 11b).
TMR2IE
TMR2IF
DD
PCFG1
CHS3
Bit 1
INTF
RE1
—
and V
1999 Microchip Technology Inc.
TMR1IF
TMR1IE
SS
PCFG0
ADON
RBIF
Bit 0
RE0
. This requires that the
—
DD
and V
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 ----
0000 0000
0000 0000
--0x 0000
xxxx 11xx
---- -000
--11 1111
1111 1111
0000 -111
Value on:
POR,
BOR
SS
. If the input
other Resets
Value on all
0000 000u
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
--0u 0000
uuuu 11uu
---- -000
--11 1111
1111 1111
0000 -111